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1 for more information www.linear.com/lt3752 typical application features description active clamp synchronous forward controllers with internal housekeeping controller the lt ? 3752/lt3752-1 are current mode pwm controllers optimized for an active clamp forward converter topology. a dc/dc housekeeping controller is included for improved efficiency and performance. the lt3752 allows operation up to 100v input and the lt3752-1 is optimized for ap - plications with input voltages greater than 100v. a programmable volt-second clamp allows primar y switch duty cycles above 50% for high switch, transformer and rectifier utilization. active clamp control reduces switch voltage stress and increases efficiency. a synchronous output is available for controlling secondary side syn - chronous rectification. the lt3752/lt3752-1 are available in a 38-lead plastic tssop package with missing pins for high voltage spacings. 18v to 72v, 12v/12.5a, 150w active clamp isolated forward converter applications n input voltage range: lt3752: 6.5v to 100v, lt3752-1:limited only by external components n internal housekeeping dc/dc controller n programmable volt-second clamp n high efficiency control: active clamp, synchronous rectification, programmable delays n short-circuit (hiccup mode) overcurrent protection n programmable soft-start/stop n programmable ovlo and uvlo with hysteresis n programmable frequency (100khz to 500khz) n synchronizable to an external clock n offline and hv car battery isolated power supplies n 48v telecommunication isolated power supplies n industrial, automotive and military systems l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 49.9k 22.6k 1.82k 7.32k 34k 71.5k 31.6k 100k 100k 2.8k 10k 560 3.16k 100k v aux v aux sync v in gnd fb lt8311 pgood 2k 0.006 10k 0.15 499 2.2f 2.2f intv cc v aux zvn4525e6 100 1.1k 1.2k 2.2nf efficiency: 94% at 48v in /10a out 0.33f 22nf 22nf 4.7f 2.2f 22f 16v 2 v out 12v 12.5a 470f 16v 4.7f 220nf 3752 ta01 68pf 4.7nf 220pf 1f t ao t as t os t blnk ivsec rt ss1 ss2 hcomp fb comp opto intv cc timer ss comp csp pmode intv cc intv cc sout i sensen i sensep out v in aout hi sense hout oc 5.9k 100k uvlo_v sec lt3752 sync 100nf 15nf si2325ds 4:4 bsc077n12ns3 fdms86101 bsc077n12ns3 499k 13.7k 6.8h 100k 11.3k csn fg f sw c g c sw 100 100 + ?? ?? ? ? ? 4.7f 100v 3 v in 18v to 72v gnd ovlo hfb 68pf lt3752/lt3752-1 3752fb
2 for more information www.linear.com/lt3752 table of contents features ..................................................... 1 applications ................................................ 1 t ypical application ........................................ 1 description .................................................. 1 table of contents .......................................... 2 absolute maximum ratings .............................. 3 order information .......................................... 3 pin configuration .......................................... 3 electrical characteristics ................................. 4 pin functions .............................................. 13 block diagram ............................................. 15 t iming diagrams ......................................... 16 operation ................................................... 19 introduction ....................................................... 19 l t3752 part start-up ......................................... 19 l t3752-1 part start-up ...................................... 19 applications information ................................ 21 p rogramming system input undervoltage lockout (uvlo) threshold and hysteresis ...................... 21 s oft-stop shutdown ........................................... 21 m icropower shutdown ....................................... 21 p rogramming system input overvoltage lockout (ovlo) threshold ............................................... 21 l t3752-1 micropower start-up from high system input voltages .................................................... 22 p rogramming switching frequency .................... 23 s ynchronizing to an external clock .................... 23 in tv cc regulator bypassing and operation ...... 24 ho usekeeping controller .............................. 24 ho usekeeping: operation .................................... 25 h ousekeeping: soft-start/shutdown .................. 25 h ousekeeping: programming output voltage ..... 25 h ousekeeping: programming cycle-by-cycle peak inductor current and slope compensation ......... 25 ho usekeeping: adaptive leading edge blanking . 26 h ousekeeping: overcurrent hiccup mode ........... 26 h ousekeeping: output overvoltage and power good .................................................................. 26 h ousekeeping: transformer turns ratio and leakage inductance ............................................ 26 h ousekeeping: operating without this supply ... 27 f orward controller ....................................... 27 a daptive leading edge blanking plus programmable extended blanking...................... 27 current sensing and programmable slope compensation .................................................... 28 o vercurrent: hiccup mode .................................. 28 p rogramming maximum duty cycle clamp: d vsec (volt-second clamp) .......................................... 29 d vsec open loop control: no opto-coupler, error amplifier or reference ........................................ 30 r ivsec : open pin detection provides safety ....... 30 tr ansformer reset: active clamp technique ..... 30 l o side active clamp topology (lt3752) ........... 32 h i side active clamp topology (lt3752-1) ......... 33 a ctive clamp capacitor value and voltage ripple .................................................... 33 a ctive clamp mosfet selection ........................ 34 p rogramming active clamp switch timing: aout to out (t ao ) and out to aout (t oa ) delays ....... 35 p rogramming synchronous rectifier timing: sout to out (t so ) and out to sout (t os ) delays ................................................................. 35 s oft-start (ss1, ss2) ......................................... 36 s oft-stop (ss1) .................................................. 36 h ard-stop (ss1, ss2) ......................................... 37 o ut, aout, sout pulse-skipping mode ............ 37 ao ut timeout .................................................... 38 m ain transformer selection ............................... 38 pr imary-side power mosfet selection ............. 40 s ynchronous control (sout) ............................. 40 o utput inductor value ......................................... 41 o utput capacitor selection ................................. 41 i nput capacitor selection ................................... 41 p cb layout / thermal guidelines ...................... 42 t ypical applications ...................................... 44 package description ..................................... 50 revision history .......................................... 51 t ypical application ....................................... 52 related parts .............................................. 52 lt3752/lt3752-1 3752fb
3 for more information www.linear.com/lt3752 pin configuration absolute maximum ratings v in (lt3752) ........................................................... 10 0v uvlo_v sec , ovlo .................................................... 2 0v v in (lt3752-1) ................................................. 1 6v, 8ma intv cc , ss2 .............................................................. 16v fb, sync .................................................................... 6v s s1, comp, hcomp, hfb, rt ..................................... 3v i sensep , i sensen , oc, hi sense ................................ 0.3 5v ivsec .................................................................. C 250a operating junction temperature range (notes 2, 3) lt 3752efe, lt3752efe-1 .................. C 40c to 125c lt3 752ife, lt3752ife-1 .................... C 40c to 125c lt3 752hfe, lt3752hfe-1 ................. C 40c to 150c lt 3752mpfe, lt3752mpfe-1 ............ C 55c to 150c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec) .................. 3 00c (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 top view fe package variation: fe38(31) 38-lead plastic tssop 38 37 36 34 32 30 28 26 24 22 21 20 hfb hcomp rt fb comp sync ss1 ivsec unlo_v sec ovlo t ao t as t os t blnk nc nc ss2 gnd pgnd pgnd nc hi sense hout aout sout v in intv cc out oc i sensep i sensen 39 pgnd gnd ja = 25c/w exposed pad (pin 39) is pgnd and gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range lt3752efe#pbf lt3752efe#trpbf lt3752fe 38-lead plastic tssop C40c to 125c lt3752ife#pbf lt3752ife#trpbf lt3752fe 38-lead plastic tssop C40c to 125c lt3752hfe#pbf lt3752hfe#trpbf lt3752fe 38-lead plastic tssop C40c to 150c lt3752mpfe#pbf lt3752mpfe#trpbf lt3752fe 38-lead plastic tssop C55c to 150c lt3752efe-1#pbf lt3752efe-1#trpbf lt3752fe-1 38-lead plastic tssop C40c to 125c lt3752ife-1#pbf lt3752ife-1#trpbf lt3752fe-1 38-lead plastic tssop C40c to 125c lt3752hfe-1#pbf lt3752hfe-1#trpbf lt3752fe-1 38-lead plastic tssop C40c to 150c lt3752mpfe-1#pbf lt3752mpfe-1#trpbf lt3752fe-1 38-lead plastic tssop C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ lt3752/lt3752-1 3752fb
4 for more information www.linear.com/lt3752 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, uvlo_v sec = 2.5v. parameter conditions min typ max units operational input voltage (lt3752) l 6.5 100 v operational input voltage (lt3752-1) l 10.5 16 v v in(on) (lt3752) l 5.8 6.4 v v in(off) (lt3752) 5.5 5.9 v v in(on/off) hysteresis (lt3752) l 0.1 0.3 0.5 v v in(on) (lt3752-1) l 9.5 10.4 v v in(off) (lt3752-1) 7.6 v v in(on/off) hysteresis (lt3752-1) l 1.61 1.9 2.19 v v in start-up current (lt3752-1) (notes 6, 7) l 170 265 a v in quiescent current (housekeeping controller only) (lt3752) hcomp = 1v (housekeeping not switching), hfb = 0.85v l 4 6.2 ma v in quiescent current (housekeeping controller only) (lt3752-1) hcomp = 1v (housekeeping not switching), hfb = 0.85v l 3 4.6 ma v in quiescent current (housekeeping controller + forward controller) hcomp = 1v (housekeeping not switching), hfb = 1.35v, fb = 1.5v (main loop not switching) 7.5 9.5 ma uvlo_v sec micropower threshold (v sd ) i vin < 20a l 0.2 0.4 0.6 v v in shutdown current (micropower) uvlo_v sec = 0.2v 20 40 a uvlo_v sec threshold (v sys_uv ) l 1.180 1.250 1.320 v v in shutdown current (after soft-stop) uvlo_v sec = 1v 165 220 a uvlo_v sec (on) current uvlo_v sec = v sys_uv + 50mv 0 a uvlo_v sec (off) current hysteresis current with one-shot communication current uvlo_v sec = v sys_uv C 50mv (note 15) l 4.0 5 25 6.0 a a ovlo (rising) (no switching, reset ss1) l 1.220 1.250 1.280 v ovlo (falling) (restart ss1) 1.215 v ovlo hysteresis l 23 35 47 mv ovlo pin current (note 10) ovlo = 0v ovlo = 1.5v (ss1 = 2.7v) ovlo = 1.5v (ss1 = 1.0v) 5 0.9 5 100 100 na ma na oscillator (forward controller: out , sout, aout) frequency: f osc = 100khz r t = 82.5k 94 100 106 khz frequency: f osc = 300khz r t = 24.9k l 279 300 321 khz frequency: f osc = 500khz r t = 14k 470 500 530 khz f osc line regulation r t = 24.9k 6.5v < v in < 100v (lt3752) 10.5v < v in < 16v (lt3752-1) 0.05 0.05 0.1 0.1 %/v %/v frequency and d vsec foldback ratio (lt3752) (fold) ss1 = v ssact + 25mv, ss2 = 2.7v 4 frequency and d vsec foldback ratio (lt3752-1) (fold) ss1 = v ss1act + 25mv, ss2 = 2.7v 2 sync input high threshold (note 4) l 1.2 1.8 v sync input low threshold (note 4) l 0.6 1.025 v sync pin current sync = 6v 75 a sync frequency/programmed f osc 1.0 1.25 khz/khz linear regulator (intv cc ) (lt3752) intv cc regulation voltage 6.6 7 7.2 v dropout (v in -intv cc ) v in = 6.5v, i intvcc = 10ma 0.8 v intv cc uvlo(+) (start switching) 4.75 5 v lt3752/lt3752-1 3752fb
5 for more information www.linear.com/lt3752 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, uvlo_v sec = 2.5v. parameter conditions min typ max units intv cc uvlo(C) (stop switching) 4.6 4.85 v intv cc uvlo hysteresis 0.075 0.15 0.24 v linear regulator (intv cc ) (lt3752-1) intv cc regulation voltage 9.4 10 10.4 v dropout (v in -intv cc ) v in = 8.75v, i intvcc = 10ma 0.6 v intv cc uvlo(+) (start switching) 7 7.4 v intv cc uvlo(C) (stop switching) 6.8 7.2 v intv cc uvlo hysteresis 0.1 0.2 0.3 v linear regulator (intv cc ) (lt3752/lt3752-1) intv cc ovlo(+) (stop switching) 15.9 16.5 17.2 v intv cc ovlo(C) (start switching) 15.4 16 16.7 v intv cc ovlo hysteresis 0.38 0.5 0.67 v intv cc current limit intv cc = 0v intv cc = 5.75v (lt3752) intv cc = 8.75v (lt3752-1) l l 17 35 35 23 50 50 29 60 60 ma ma ma error amplifier fb reference v oltage l 1.220 1.250 1.275 v fb line reg 6.5v < v in < 100v (lt3752) 10.5v < v in < 16v (lt3752-1) 0.1 0.1 0.3 0.3 mv/v mv /v fb load reg comp_sw C 0.1v < comp < comp_v oh C 0.1v 0.1 0.3 mv/v fb input bias current (note 10) 50 200 na open-loop voltage gain 85 db unity-gain bandwidth (note 8) 2.5 mhz comp source current fb = 1v, comp = 1.75v (note 10) 6 11 ma comp sink current fb = 1.5v, comp = 1.75v 6.5 11.5 ma comp output high clamp fb = 1v 2.6 v comp switching threshold 1.25 v current sense (main loop) i sensep maximum threshold fb = 1v, oc = 0v 180 220 260 mv comp current mode gain ?v comp /?v isensep 6.1 v/v i sensep input current (d = 0%) (note 10) 2 a i sensep input current (d = 80%) (note 10) 33 a i sensen input current fb = 1.5v (comp open) (note 10) fb = 1v (comp open) (note 10) 20 90 30 135 a a oc over current threshold l 82.5 96 107.5 mv oc input current 200 500 na aout driver (active clamp switch control) (lt3752 external pmos; lt3752-1 external nmos) aout rise time c l = 1nf (note 5), intv cc = 12v 23 ns aout fall time c l = 1nf (note 5), intv cc = 12v 19 ns aout low level 0.1 v aout high level intv cc = 12v 11.9 v aout high level in shutdown (lt3752) uvlo_v sec = 0v, intv cc = 8v, i aout = 1ma out of the pin 7.8 v aout low level in shutdown (lt3752-1) uvlo_v sec = 0v, intv cc = 12v, i aout = 1ma into the pin 0.25 v lt3752/lt3752-1 3752fb
6 for more information www.linear.com/lt3752 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, uvlo_v sec = 2.5v. parameter conditions min typ max units aout edge to out (rise): (t ao ) c sout = 1nf, c out = 3.3nf, intv cc = 12v r tao = 44.2k r tao = 73.2k (note 11) 168 253 218 328 268 403 ns ns out (fall) to aout edge: (t oa ) c sout = 1nf, c out = 3.3nf, intv cc = 12v r tao = 44.2k r tao = 73.2k (note 12) 150 214 196 295 250 376 ns ns sout driver (synchronous rectification control) sout rise time c out = 1nf, intv cc = 12v (note 5) 21 ns sout fall time c out = 1nf, intv cc = 12v (note 5) 19 ns sout low level 0.1 v sout high level intv cc = 12v 11.9 v sout high level in shutdown uvlo_v sec = 0v, intv cc = 8v, i sout = 1ma out of the pin 7.8 v aout edge to sout (fall): (t as ) c aout = c sout = 1nf, intv cc = 12v r tas = 44.2k (note 13) r tas = 73.2k 168 253 218 328 268 403 ns ns sout (fall) to out (rise): (t so = t ao C t as ) c sout = 1nf, c out = 3.3nf, intv cc = 12v r tao = 73.2k, r tas = 44.2k (notes 11, 13) r tao = 44.2k, r tas = 73.2k 70 C70 110 C110 132 C132 ns ns out (fall) to sout (rise): (t os ) c sout = 1nf, c out = 3.3nf, intv cc = 12v r tos = 14.7k r tos = 44.2k (note 14) 52 102 68 133 84 164 ns ns out driver (main power switch control) out rise time c out = 3.3nf, intv cc = 12v (note 5) 19 ns out fall time c out = 3.3nf, intv cc = 12v (note 5) 20 ns out low level 0.1 v out high level intv cc = 12v 11.9 v out low level in shutdown uvlo_v sec = 0v, intv cc = 8v, i out = 1ma into the pin 0.25 v out (volt-sec) max duty cycle clamp d vsec (1 ? system input (min)) 100 d vsec (2 ? system input (min)) 100 d vsec (4 ? system input (min)) 100 r t = 24.9k, r ivsec = 51.1k, fb = 1v, ss1 = 2.7v uvlo_v sec = 1.25v uvlo_v sec = 2.50v uvlo_v sec = 5.00v 68.5 34.3 17.5 72.5 36.5 18.6 76.2 38.7 19.7 % % % out minimum on t ime c out = 3.3nf, intv cc = 12v (note 9) r tblnk = 14.7k r tblnk = 73.2k (note 16) 325 454 ns ns ss1 pin (soft-start: frequency and d vsec ) (soft-stop: comp pin, frequency and d vsec ) ss1 reset threshold (v ss1(rth) ) 150 mv ss1 active threshold (v ss1(act) ) (allow switching) 1.25 v ss1 charge current (soft-start) ss1 = 1.5v (note 10) 7 11.5 16 a ss1 discharge current (soft-stop) ss1 = 1v, uvlo_v sec = v sys_uv C 50mv 6.4 10.5 14.6 a ss1 discharge current (hard stop) oc > oc threshold intv cc < intv cc uvlo(C) ovlo > ovlo(+) ss1 = 1v 0.9 0.9 0.9 ma ma ma ss2 pin (soft-start: comp pin) ss2 discharge current ss1 < v ss(act) , ss2 = 2.5v 2.8 ma ss2 charge current ss1 > v ss(act) , ss2 = 1.5v 11 21 28 a lt3752/lt3752-1 3752fb
7 for more information www.linear.com/lt3752 parameter conditions min typ max units error amplifier (housekeeping controller) hfb reference voltage 0.90 1.000 1.10 v hfb line reg 6.5v < v in < 100v (lt3752) 10.5v < v in < 16v (lt3752-1) 0.1 0.1 mv/v mv /v hfb load reg hcomp v sw C 0.1v < hcomp < hcomp v oh C 0.1v C6 mv/v hfb input bias current hfb = 1.1v (note 10) 85 170 na transconductance ?i hcomp 5a 250 s voltage gain 175 v/v power good(+) (hfb level) 0.96 v power good(C) (hfb level) 0.92 v hfb ovlo(+) (disable hout switching) 1.206 v hfb ovlo(C) (enable housekeeping operation) 1.150 v hcomp source current hcomp = 1.75v (note 10) 11 15 19 a hcomp sink current hcomp = 1.75v 13 18 23 a hcomp output high clamp 2.9 v hcomp switching threshold 1.28 v current sense (housekeeping controller) hi sense peak current threshold hfb = 0.8v 69 79 86.5 mv hcomp current mode gain ?v hcomp /?v hisense 9.1 v/v hi sense input current (d = 0%) hi sense input current (d = 80%) (note 10) 2 52 a a hi sense overcurrent threshold 84.6 98 105.4 mv hout driver (housekeeping controller) hout rise time c l = 1nf (note 5), intv cc = 12v 13 ns hout fall time c l = 1nf (note 5), intv cc = 12v 12 ns hout low level 0.1 v hout high level lt3752 lt3752-1 intv cc = 12v 11.9 11.9 v v hout low level in shutdown uvlo_v sec = 0v, intv cc = 12v, i hout = 1ma into the pin 0.25 v hout maximum duty cycle hcomp = 2.7v, r t = 24.9k 90 95 % hout minimum on time c l = 1nf (note 9), intv cc = 12v 350 ns soft-start (hss) (housekeeping controller) hss (internal) ramp time (t hss ) hcomp sw hcomp v oh C 0.1v 2.2 4 ms oscillator (housekeeping controller) frequency (f hout ) (f osc folded back) (lt3752) hfb = 0.8v, r t = 24.9k, ss1 = 0v 55 65 75 khz frequency (f hout ) (f osc folded back) (lt3752-1) hfb = 0.8v, r t = 24.9k, ss1 = 0v 119 141 163 khz frequency (f hout ) (full-scale f osc ) hfb = 1.15v, hcomp = 2.7v l 279 300 321 khz electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, uvlo_v sec = 2.5v. lt3752/lt3752-1 3752fb
8 for more information www.linear.com/lt3752 electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3752efe/lt3752efe-1 are guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3752ife/lt3752ife-1 are guaranteed to meet performance specifications from C40c to 125c junction temperature. the lt3752hfe/ lt3752hfe-1 are guaranteed to meet performance specifications from C40c to 150c junction temperature. the lt3752mpfe/lt3752mpfe-1 are tested and guaranteed to meet performance specifications from C55c to 150c junction temperature. note 3: for maximum operating ambient temperature, see the thermal calculations section in the applications information section. note 4: sync minimum and maximum thresholds are guaranteed by sync frequency range test using a clock input with guard banded sync levels of 0.7v low level and 1.7v high level. note 5: rise and fall times are measured between 10% and 90% of gate driver supply voltage. note 6: guaranteed by correlation to static test. note 7: v in start-up current is measured at v in = v in(on) C 0.25v and then scaled by 1.18 to correlate to worst-case v in current required for part start-up at v in = v in(on) . note 8: guaranteed by design. note 9: on times are measured between rising and falling edges at 50% of gate driver supply voltage. note 10: current flows out of pin. note 11: guaranteed by correlation to r tas = 73.2k test. note 12: t oa timing guaranteed by design based on correlation to measured t ao timing. note 13: guaranteed by correlation to r tao = 44.2k test. note 14: guaranteed by correlation to r tos = 14.7k test. note 15: a 2s one-shot of 20a from the uvlo_v sec pin allows communication between ics to begin shutdown (useful when stacking supplies for more power ( = inputs in parallel/outputs in series)). the current is tested in a static test mode. the 2s one-shot is guaranteed by design. note 16: guaranteed by correlation to r tblnk = 14.7k test. lt3752/lt3752-1 3752fb
9 for more information www.linear.com/lt3752 v in start-up and shutdown current vs junction temperature v in(on) , v in(off) thresholds vs junction temperature v in quiescent current vs junction temperature uvlo_vsec turn-on threshold vs junction temperature uvlo_v sec hysteresis current vs junction temperature hfb pgood thresholds vs junction temperature typical performance characteristics t a = 25c, unless otherwise noted. junction temperature (c) ?75 v in current (a) 220 180 200 160 140 120 100 80 60 40 20 0 25 150 ?25 100 3752 g01 175 0 125 ?50 50 75 lt3752-1 v in start-up current (v in = v in_on ) lt3752/lt3752-1 v in shutdown current (v in = 12v) uvlo_vsec = 0.2v junction temperature (c) ?75 uvlo_vsec threshold (v) 1.275 1.270 1.265 1.260 1.255 1.250 1.245 1.240 1.235 1.230 1.225 25 150 ?25 100 3752 g04 175 0 125 ?50 50 75 junction temperature (c) ?75 hfb pgood thresholds (v) 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 25 150 ?25 100 3752 g06 175 0 125 ?50 50 75 hfb pgood (+) = enable forward controller circuitry hfb pgood (?) = disable forward controller circuitry junction temperature (c) ?75 uvlo_vsec hysteresis current (a) 6.0 5.5 5.0 4.5 4.0 25 150 ?25 100 3752 g05 175 0 125 ?50 50 75 junction temperature (c) ?75 v in i q (ma) 8 7 6 5 4 3 2 1 0 25 150 ?25 100 3752 g03 175 0 125 ?50 50 75 lt3752: housekeeping only (no switching) lt3752/-1: housekeeping + forward (no switching) lt3752-1: housekeeping only (no switching) junction temperature (c) ?75 v in on/off thresholds (v) 10.0 9.0 9.5 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 25 150 ?25 100 3752 g02 175 0 125 ?50 50 75 lt3752-1 vin_on lt3752-1 vin_off lt3752 vin_on lt3752 vin_off hfb reference voltage vs junction temperature hfb ovlo thresholds vs junction temperature junction temperature (c) ?75 hfb ovlo thresholds (v) 1.30 1.25 1.20 1.15 1.10 1.05 1.00 25 150 ?25 100 3752 g08 175 0 125 ?50 50 75 hfb > ovlo (+) = disable hout switching hfb < ovlo (?) = enable housekeeping operation junction temperature (c) ?75 hfb reference voltage (v) 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 25 150 ?25 100 3752 g07 175 0 125 ?50 50 75 lt3752/lt3752-1 3752fb
10 for more information www.linear.com/lt3752 lt3752-1: intv cc in dropout at v in = 8.75v vs current, junction temperature lt3752: intv cc in dropout at v in = 6.5v vs current, junction temperature lt3752: intv cc uvlo thresholds vs junction temperature lt3752: intv cc regulation voltage vs current, junction temperature typical performance characteristics t a = 25c, unless otherwise noted. junction temperature (c) ?75 intv cc (v) 7.0 6.5 6.0 5.5 5.0 3.5 4.5 4.0 3.0 25 150 ?25 100 3752 g13 175 0 125 ?50 50 75 i load = 0ma i load = 10ma i load = 15ma i load = 20ma junction temperature (c) ?75 intv cc (v) 7.00 6.95 6.90 6.85 6.80 6.65 6.75 6.70 6.60 25 150 ?25 100 3752 g15 175 0 125 ?50 50 75 i load = 0ma i load = 10ma i load = 20ma i load = 30ma v in = 12v junction temperature (c) ?75 intv cc (v) 10.0 9.5 9.0 8.5 7.5 8.0 5.5 7.0 6.5 6.0 5.0 25 150 ?25 100 3752 g16 175 0 125 ?50 50 75 i load = 0ma i load = 10ma i load = 15ma i load = 20ma v in = 12v hi sense peak current threshold vs junction temperature hi sense pin current vs duty cycle hi sense overcurrent (hiccup mode) threshold vs junction temperature housekeeping internal soft-start time (hss) vs junction temperature junction temperature (c) ?75 hi sense peak current threshold (mv) 85 84 83 82 81 80 79 77 76 78 75 25 150 ?25 100 3752 g09 175 0 125 ?50 50 75 duty cycle (%) 0 hi sense pin current (a) 60 50 40 30 10 20 0 40 90 20 70 3752 g10 100 30 80 10 50 60 t j = 150c t j = 25c t j = ?55c junction temperature (c) ?75 hi sense overcurrent threshold (mv) 110 105 100 95 85 90 80 25 150 ?25 100 3752 g11 175 0 125 ?50 50 75 junction temperature (c) ?75 housekeeping internal soft-start time (ms) 3.00 2.75 2.50 2.25 1.75 2.00 1.50 25 150 ?25 100 3752 g12 175 0 125 ?50 50 75 junction temperature (c) ?75 intv cc uvlo threshold (v) 4.85 4.80 4.75 4.70 4.55 4.65 4.60 4.50 25 150 ?25 100 3752 g14 175 0 125 ?50 50 75 intv cc < uvlo (?): disable switching intv cc > uvlo (+): enable switching lt3752/lt3752-1 3752fb
11 for more information www.linear.com/lt3752 lt3752-1: intv cc uvlo thresholds vs junction temperature ss1 soft-start/soft-stop pin currents vs junction temperature ss1 high, active and reset levels vs junction temperature ss2 soft-start charge current vs junction temperature lt3752-1: intv cc regulation voltage vs current, junction temperature typical performance characteristics t a = 25c, unless otherwise noted. junction temperature (c) ?75 intv cc (v) 10.00 9.95 9.90 9.85 9.80 9.65 9.75 9.70 9.40 9.60 9.55 9.50 9.45 25 150 ?25 100 3752 g18 175 0 125 ?50 50 75 i load = 0ma i load = 10ma i load = 20ma i load = 30ma v in = 12v junction temperature (c) ?75 ss2 soft-start charge current (a) 25 24 23 16 22 21 20 19 18 17 15 25 150 ?25 100 3752 g21 175 0 125 ?50 50 75 ss2 pin current* (?1) junction temperature (c) ?75 ss1 currents (a) 14.0 13.5 13.0 12.5 8.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.0 25 150 ?25 100 3752 g19 175 0 125 ?50 50 75 ss1 soft-start: charge current* (?1) ss1 soft-stop: discharge current junction temperature (c) ?75 ss1 high, active and reset levels (v) 3.00 2.75 2.50 2.25 0.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0 25 150 ?25 100 3752 g20 175 0 125 ?50 50 75 ss1 active level (allow forward converter switching) ss1 high level ss1 reset level (reset ss1 latch) switching frequency vs ss1 pin voltage switching frequency vs junction temperature junction temperature (c) ?75 switching frequency (khz) 325 320 315 280 310 305 300 295 290 285 275 25 150 ?25 100 3752 g23 175 0 125 ?50 50 75 r t = 24.9k fb reference voltage vs junction temperature junction temperature (c) ?75 fb reference voltage (v) 1.30 1.29 1.28 1.21 1.27 1.26 1.25 1.24 1.23 1.22 1.20 25 150 ?25 100 3752 g24 175 0 125 ?50 50 75 junction temperature (c) ?75 intv cc uvlo thresholds (v) 7.20 7.15 7.10 7.05 6.65 7.00 6.95 6.90 6.85 6.80 6.75 6.70 6.60 25 150 ?25 100 3752 g17 175 0 125 ?50 50 75 intv cc < uvlo (?): disable forward converter switching intv cc > uvlo (+): enable forward converter switching ss1 (v) 0 switching frequency (khz) 350 325 300 275 25 250 225 200 175 150 100 75 125 50 0 1 2.25 2.5 0.5 1.75 3752 g22 2.75 0.75 2 0.25 1.25 1.5 r t = 24.9k lt3752-1 f (hout) f (out) f (hout)lt3752-1 f (hout)lt3752 f (out) lt3752 f (hout) f (out) lt3752/lt3752-1 3752fb
12 for more information www.linear.com/lt3752 typical performance characteristics t a = 25c, unless otherwise noted. sout (fall) to out (rise) delay (t so = t ao C t as ) vs junction temperature out (fall) to sout (rise) delay (t os ) vs junction temperature junction temperature (c) ?75 t so (ns) 160 140 80 60 40 120 100 20 25 150 ?25 100 3752 g32 175 0 125 ?50 50 75 r tos = 44.2k r tos = 14.7k r tos = 7.32k junction temperature (c) ?75 t so (ns) 120 80 100 60 ?20 ?40 ?60 ?80 ?100 40 20 0 ?120 25 150 ?25 100 3752 g31 175 0 125 ?50 50 75 r tao = 73.2k, r tas = 44.2k r tao = 44.2k, r tas = 73.2k i sensep maximum threshold vs comp extended blanking duration vs junction temperature aout to sout delay (t as ) vs junction temperature aout to out delay (t ao ) and out to aout delay (t oa ) vs junction temperature i sensep maximum threshold C vslp vs duty cycle (programming slope compensation) oc overcurrent (hiccup mode) threshold vs junction temperature junction temperature (c) ?75 oc overcurrent threshold (mv) 110 105 100 85 95 90 80 25 150 ?25 100 3752 g27 175 0 125 ?50 50 75 junction temperature (c) ?75 t ao and t ca (ns) 340 300 320 280 200 180 160 260 240 220 140 25 150 ?25 100 3752 g29 175 0 125 ?50 50 75 r tao = 73.2k t ao r tao = 44.2k t oa t ao t oa comp (v) 1.2 i sensep threshold (mv) 240 220 200 20 180 160 140 120 60 100 80 40 0 2.42.2 3752 g25 2.6 1.61.4 1.8 2 oc threshold duty cycle (%) 0 i sensep maximum threshold - vslope (v) 240 220 200 180 160 140 9080 3752 g26 100 2010 30 40 50 60 70 r islp = 0 vslp = i(i sensep ) ? r islp r islp = 1.5k r islp = 2k junction temperature (c) ?75 t as (ns) 340 300 320 280 200 180 160 260 240 220 140 25 150 ?25 100 3752 g30 175 0 125 ?50 50 75 r tas = 73.2k r tas = 44.2k junction temperature (c) ?75 extended blanking duration (ns) 220 200 180 100 80 160 140 120 60 25 150 ?25 100 3752 g28 175 0 125 ?50 50 75 r tblnk = 73.2k r tblnk = 14.7k lt3752/lt3752-1 3752fb
13 for more information www.linear.com/lt3752 typical performance characteristics t a = 25c, unless otherwise noted. required r ivsec vs switching frequency (for d vsec 100 = 72.5%, uvlo_vsec = 1.25v) out pin rise/fall times vs out pin load capacitance out maximum duty cycle clamp (d vsec ) vs uvlo_v sec switching frequency (khz) 100 programmed r ivsec (k) 160 140 80 60 40 20 120 100 0 250 450400 3752 g34 500 200150 300 350 out pin load capacitance (nf) 0 out pin rise/fall times (ns) 60 50 30 20 10 40 0 3 8 97 3752 g35 10 21 4 65 intv cc = 12v (overdriven from housekeeping supply) uvlo_vsec (v) 0 id vsec 100 (%) 80 70 40 30 20 10 60 50 0 3.75 8.757.5 3752 g33 10 2.51.25 5 6.25 v in = 12v r t = 24.9k (300khz) r ivsec = 51.1k pin functions hfb (pin 1): housekeeping supply error amplifier inverting input. hcomp (pin 2): housekeeping supply error amplifier output and compensation pin. r t (pin 3): a resistor to ground programs switching frequency. fb (pin 4): error amplifier inverting input. comp (pin 5): error amplifier output. allows various compensation networks for nonisolated applications. sync (pin 6): allows synchronization of internal oscillator to an external clock. f sync equal to f osc allowed. ss1 (pin 7): capacitor controls soft-start/stop of switch - ing frequency and volt-second clamp. during soft-stop it also controls the comp pin. ivsec (pin 8): resistor programs out pin maximum duty cycle clamp (d vsec ). this clamp moves inversely proportional to system input voltage to provide a volt- second clamp. uvlo_v sec (pin 9): a resistor divider from system in- put allows switch maximum duty cycle to vary inversely proportional with system input. this volt-second clamp prevents transformer saturation for duty cycles above 5 0 %. resistor divider ratio programs undervoltage lockout (uvlo) threshold. a 5a pin current hysteresis allows programming of uvlo hysteresis. pin below 0.4v reduces v in currents to microamps. ovlo (pin 10): a resistor divider from system input programs overvoltage lockout (ovlo) threshold. fixed hysteresis included. t ao (pin 11): a resistor programs nonoverlap timing between aout rise and out rise control signals. t as (pin 12): resistors at t ao and t as define delay between sout fall and out rise (= t ao C t as ). t os (pin 13): resistor programs delay between out fall and sout rise. t blnk (pin 14): resistor programs extended blanking of i sensep and oc signals during mosfet turn-on. nc (pins 15, 16, 37): no connect pins. these pins are not connected inside the ic. these pins should be left open. ss2 (pin 17): capacitor controls soft-start of comp pin. alternatively can connect to opto to communicate start of switching to secondary side. if unused, leave the pin open. gnd (pin 18): analog signal ground. electrical connection exists inside the ic to the exposed pad (pin 39). lt3752/lt3752-1 3752fb
14 for more information www.linear.com/lt3752 pgnd (pins 19, 38, 39): the power grounds for the ic. the package has an exposed pad (pin 39) underneath the ic which is the best path for heat out of the package. pin 39 should be soldered to a continuous copper ground plane under the device to reduce die temperature and increase the power capability of the lt3752/lt3752-1. i sensen (pin 20): negative input for the current sense comparator. kelvin connect to the sense resistor in the source of the power mosfet. i sensep (pin 21): positive input for the current sense comparator. kelvin connect to the sense resistor in the source of the power mosfet. a resistor in series with i sensep programs slope compensation. oc (pin 22): an accurate 96mv threshold, independent of duty cycle, for detection of primary side mosfet over - current and trigger of hiccup mode. connect directly to sense resistor in the source of the primar y side mosfet. missing pins 23, 25, 27, 29, 31, 33, 35: pins removed for high voltage spacings and improved reliability. out (pin 24): drives the gate of an n-channel mosfet between 0v and intv cc . active pull-off exists in shutdown. intv cc (pin 26): a linear regulator supply generated from v in . lt3752 supplies 7v for aout, sout, out and hout gate drivers. lt3752-1 supplies 10v for aout,sout, and out gate drivers (hout supplied from v in ). intv cc must be bypassed with a 4.7f capacitor to power ground. can be externally driven by the housekeeping supply to remove power from within the ic. v in (pin 28): input supply pin. bypass with 1f to ground. sout (pin 30): sync signal for secondary side synchro - nous rectifier controller. aout (pin 32): control signal for external active clamp switch. (p-channel lt3752, n-channel lt3752-1). hout (pin 34): drives the gate of an n-channel mosfet used for the housekeeping supply. active pull-off exists in shutdown. hi sense (pin 36): current sense input for the house keep - ing supply. connect to sense resistor in the source of the power mosfet . a resistor in series with hi sense programs slope compensation. pin functions lt3752/lt3752-1 3752fb
15 for more information www.linear.com/lt3752 block diagram part system input max v in pin max v in on/off intv cc uvlo(+)/(reg) aout phasing l t3752 100v 100v 5.8v /5.5v 4.75v/7v for external pmos lt3752-1 limited only by external components 16v, 8ma (internal v in clamp) 9.5v/7.6v 7v/10v for external nmos + ? + ? 1.25v + ? + ? + ? + ? 1.25v (+) 1.215v (?) en_ss1 uvlo_v sec en pgood hislp out 0.4v 5a 0.9ma ss1 > 1.25v hard stop v in_on v in_off v in soft stop ss1 < 150mv 20a (1 shot) uvlo_v sec 9 hfb 1.0v 1.25v 1 hcomp housekeeping controller hi sense 79mv clamp 2 36 hout 34 v in ovlo 10 ivsec 8 sync 100k 6 rt 3 ss2 17 ss1 fb 7 4 comp 5 t ao 11 t as 12 t os 13 t blnk gnd (+ exposed pad pin 39) (+ exposed pad pin 39) 14 18 pgnd (19, 38) + ? + ? + ? + ? 1.25v ref + ? hss hislp hiccup 98mv 0.7a 0.4a 0.4a 2a 1.25v + ? r osc fold back islp 1.25v 150mv hard stop soft start ss2 1.25v ss1 en_ss1 (0220)mv soft stop ss1 > 2.2v v sec clamp timing logic s q s r q s q ss1 < 1.25v t j > 170c intv cc_ov intv cc_uv r + ? + ? + ? + ? 28 intv cc 26 aout off on 96mv off fg cg on active clamp control synchronous control main switch 32 sout 30 out 24 oc 22 i sensep 21 i sensen 3752 bd 20 ea blank islp hiccup (invert level for lt3752-1) control r s q lt3752/lt3752-1 3752fb
16 for more information www.linear.com/lt3752 timing diagrams t ao t as aout m1 m4 fg cg sync m3 swp ltxxxx csw fsw gnd sout ? ? ? ? m2 ?v in v in ?v out 3752 f02 v out lt3752 out t os figure 1. lt3752 timing diagram (lt3752-1 inverts aout phase for n-channel control) figure 2. timing reference circuit t oa t ao t so t as t os 0v aout out swp sout cg fg fsw csw t (1/f osc ) t ao programmed by r tao , t as programmed by r tas t os programmed by r tos , t oa = 0.9 ? t ao , t so = t ao ? t as 0v 0v 0v 0v 0v v out /(1 ? duty cycle) v in /(1 ? duty cycle) 0v 0v 3752 f01 v in lt3752/lt3752-1 3752fb
17 for more information www.linear.com/lt3752 timing diagrams figure 3. lt3752 start-up and shutdown timing diagram system input (min) +v hyst 1.25v 0v 0v 0v 0v 0v 0v 0v 0hz 7v (reg) 150mv 1.25v 4.75v uvlo(+) pgood(+) (96% of full-scale v hk ) completed soft-stop shutdown: 0.6v < uvlo_v sec < 1.25v and ss1 < 150mv ss1 soft starts f osc and dv sec ss2 soft starts comp ss1 soft stops f osc , dv sec and comp optional bootstrap diode from v hk system input (min) system input (lt3752 v in pin) uvlo_v sec (resistor divider from system input) v hk (housekeeping supply output) ss1 comp ss2 f osc (switching frequency) intv cc trigger soft stop comp switching threshold 1.25v full-scale f osc 3752 f03 aout, out, sout switching hout switching full-scale f osc /4.6 lt3752/lt3752-1 3752fb
18 for more information www.linear.com/lt3752 figure 4. lt3752-1 start-up and shutdown timing diagram timing diagrams trigger soft stop system input (min) +v hyst 1.25v 0v system input (min) system input 0v 0v 0v uvlo_v sec pin (resistor divider from system input) lt3752-1 v in pin (resistor from system input) intv cc ss1 comp ss2 f osc (switching frequency) v hk (housekeeping supply output) 16v clamp v in(on) v in(off) 10v (reg) 150mv full-scale f osc 3752 f04 full-scale f osc /2.13 1.25v 7v uvlo(+) pgood(+) (96% of full-scale v hk ) bootstrap diode from v hk optional bootstrap diode from v hk ss1 soft starts f osc and dv sec ss2 soft starts comp completed soft-stop shutdown: 0.6v < uvlo_v sec < 1.25v and ss1 < 150mv ss1 soft stops f osc , dv sec and comp comp switching threshold 1.25v aout, out, sout switching hout switching lt3752/lt3752-1 3752fb
19 for more information www.linear.com/lt3752 operation introduction the lt3752/lt3752-1 are primary side, current mode, pwm controllers optimized for use in a synchronous forward converter with active clamp reset. combined with an integrated housekeeping controller, each ic provides a compact, versatile, and highly efficient solution. the lt3752 allows v in pin operation between 6.5v and 100v. for applications with system input voltages greater than 100v, the lt3752-1 allows rc start-up from input voltage levels limited only by external components. the lt3752 and lt3752-1 based forward converters are targeted for power levels up to 400w and are not intended for battery charger applications. for higher power levels the converter outputs can be stacked in series. connecting uvlo_v sec pins, ovlo pins, ss1 pins and ss2 pins together allows blocks to react simultaneously to all fault modes and conditions. each ic contains an accurate programmable volt-second clamp. when set above the natural duty cycle of the con - verter, it provides a duty cycle guardrail to limit primary switch reset voltage and prevent transformer saturation during load transients. the accuracy and excellent line regulation of the volt-second clamp provides v out regu- lation for open-loop conditions such as no opto-coupler, reference or error amplifier on the secondar y side. for applications not requiring isolation but requiring high step-down ratios, each ic contains a voltage error ampli - fier to allow a very simple nonisolated, fully regulated synchronous for ward converter . the integrated housekeeping controller reduces the com - plexity and size of the main power transformer by avoid - ing the need for extra windings to create bias supplies. secondar y side ics no longer require start-up cir cuitry and can operate even when output voltage is 0v. a range of protection features include programmable overcurrent (oc) hiccup mode, programmable system input undervoltage lockout (uvlo), programmable system input overvoltage lockout (ovlo) and built-in thermal shutdown. programmable slope compensation and switching frequency allow the use of a wide range of output inductor values and transformer sizes. lt3752 part start-up lt3752 start-up is best described by referring to the block diagram and to the start-up waveforms in figure?3. for part start-up, system input voltage must be high enough to drive the uvlo_v sec pin above 1.25v and the v in pin must be greater than 6.5v. an internal linear regulator is activated and provides a 7v intv cc supply for all gate drivers. the housekeeping controller starts up before the forward controller. an internal soft-start (hss) ramps the housekeeping hcomp pin to allow switching at the gate driver output hout to drive an external n-channel mosfet. the housekeeping controller output voltage v hk is regulated when the hfb pin reaches 1.0v. v hk can be used to override intv cc to reduce power in the part, increase efficiency and to optimize the intv cc level. dur - ing start-up the housekeeping controller switches at the programmed switching frequency (f osc ) folded back by 1/4.6. the ss1 pin of the forward controller is allowed to start charging when v hk reaches 96% of its target value (pgood). when ss1 reaches 1.25v, the ss2 pin begins to charge, controlling comp pin rise and the soft-start of output inductor peak current. the ss1 pin independently soft starts switching frequency and a volt-second clamp. as ss1 charges towards 2.6v the switching frequencies of both controllers remain equal, synchronized and soft started towards full-scale f osc . if secondary side control already exists for soft starting the converter output voltage then the ss2 pin can still be used to control initial inductor peak current rise. simply programming the primary side ss2 soft-start faster than the secondary side allows the secondary side to take over. if ss2 is not needed for soft-start control, its pull-down strength and voltage rating also allow it to drive the input of an opto-coupler connected to intv cc . this allows the option of communicating to the secondary side that switching has begun. lt3752-1 part start-up the lt3752-1 start-up of housekeeping supply and forward converter are similar to the lt3752 except for a small change in architecture and v in pin level. lt3752 - 1 start-up is best described by referring to the block diagram and to lt3752/lt3752-1 3752fb
20 for more information www.linear.com/lt3752 operation the start-up waveforms in figure 4. the lt3752-1 starts up by using a high valued resistor from system input to charge up the input capacitor at the v in pin. if system input is already high enough to generate uvlo_v sec above 1.25v, then the part turns on once v in pin charges past v in(on) (9.5v). if system input is not high enough to generate uvlo_v sec above 1.25v, the v in pin charges towards system input until it reaches an internal 16v, 8ma clamp. the part turns on when system input becomes high enough to generate uvlo_v sec above 1.25v. as the supply current of the part discharges the v in capacitor a bootstrap supply must be generated to prevent v in pin from falling below v in(off) (7.6v). the lt3752-1 uses the housekeeping controller to provide the bootstrap bias to the v in pin during rc start-up instead of waiting for the forward converter to also start. this meth - od is more efficient, requires a smaller v in input capacitor and avoids the need for an auxiliary winding in the main transformer. the parts low start-up current at the v in pin allows the use of a large start-up resistor to minimize power loss from system input. the v in capacitor value required for proper start-up is minimized by providing a large v in(on) - v in(off) hysteresis, a low v in i q and a fast start-up time for the housekeeping controller. in contrast to the lt3752, the lt3752-1 housekeeping gate driver (hout) runs from the v in pin instead of intv cc . this avoids having to use cur - rent from the v in pin to charge the intv cc capacitor during initial start-up. this means the regulated 10v intv cc on the lt3752-1 does not wake up until the housekeeping supply is valid. start-up from this point is similar to the lt3752. the housekeeping supply and forward converter switch together with a soft-started frequency and volt-second clamp. the forward converter peak inductor current is also soft started similar to the lt3752. lt3752/lt3752-1 3752fb
21 for more information www.linear.com/lt3752 1.250v 3752 f05 r1 r2 to ovlo pin r3 system input (v s ) uvlo_v sec lt3752/lt3752-1 5a ? + figure 5. programming undervoltage lockout (uvlo) applications information programming system input undervoltage lockout (uvlo) threshold and hysteresis the lt3752/lt3752-1 have an accurate 1.25v shutdown threshold at the uvlo_v sec pin. this threshold can be used in conjunction with an external resistor divider to define the falling undervoltage lockout threshold (uvlo(C)) for the converters system input voltage (v s ) (figure 5). a pin hysteresis current of 5a allows programming of the uvlo(+) threshold. v s (uvlo(C)) [begin soft-stop then shut down] = 1.25 1 + r1 r2 + r3 ? ? ? ? ? ? ? ? ? ? ? ? v s (uvlo(+)) [begin soft-start] = v s (uvlo(C)) + (5a ? r1) it is important to note that the part enters soft-stop when the uvlo_v sec pin falls back below 1.25v. during soft- stop the converter continues to switch as it folds back switching frequency, volt-second clamp and comp pin voltage. see soft-stop in the applications information section. when the ss2 pin is finally discharged below its 150mv reset threshold both the housekeeping supply and forward converter are shut down. used to pull down the uvlo_v sec pin below 1.25v but not below the micropower shutdown threshold of 0.6v(max). typical v in quiescent current after soft-stop is 165a. micropower shutdown if a micropower shutdown is required using an external control signal, an open-drain transistor can be directly connected to the uvlo_v sec pin. the lt3752/lt3752 - 1 ha ve a micropower shutdown threshold of typically 0.4v at the uvlo_v sec pin. v in quiescent current in micropower shutdown is 20a. programming system input overvoltage lockout (ovlo) threshold the lt3752/lt3752-1 have an accurate 1.25v overvoltage shutdown threshold at the ovlo pin. this threshold can be used in conjunction with an external resistor divider to define the rising overvoltage lockout threshold (ovlo(+)) for the converters system input voltage (v s ) (figure 6). when ovlo(+) is reached, the part stops switching im - mediately and a hard stop discharges the ss1 and ss2 pins. the falling threshold ovlo(C) is fixed internally at 1.215v and allows the part to restart in soft-start mode. a single resistor divider can be used from system input supply (v s ) to define both the undervoltage and overvolt - age thresholds for the system. minimum value for r3 is 1k. if ovlo is unused, place a 10k resistor from ovlo pin to ground. v s ovlo(+) [stop switching; hard stop] = 1.25 1 + r1 + r2 r3 ? ? ? ? ? ? ? ? ? ? ? ? v s ovlo(C) [begin soft-start] = v s ovlo + ( ) ? 1.215 1.25 soft-stop shutdown soft-stop shutdown (similar to system undervoltage) can be commanded by an external control signal. a mosfet with a diode (or diodes) in series with the drain should be lt3752/lt3752-1 3752fb
22 for more information www.linear.com/lt3752 applications information figure 6. programming overvoltage lockout (ovlo) lt3752-1 micropower start-up from high system input voltages the lt3752-1 starts up from system input voltage levels limited only by external components (figure 7). the low start-up current of the lt3752-1 allows a large start-up resistor (r start ) to be connected from system input volt - age (v s ) to the v in pin. when system input voltage is applied, the start-up capacitor (c start ) begins charging at the v in pin. once the v in pin exceeds 9.5v (and uvlo_v sec > 1.25v) the housekeeping controller will start to switch and v in supply current will begin to discharge c start . the c start capacitor value should be chosen high enough to prevent the v in pin from falling below 7.6v before the housekeeping supply can provide a bootstrap bias to the v in pin. the lt3752 - 1 start-up architecture minimizes the value of c start by activating only the house keeping controller for provid - ing drive back to the v in pin. the forward controller only operates once the housekeeping supply is established. (if a bootstrap diode is used from the housekeeping supply back to intv cc , this only uses current from system input and not from the v in pin). 1.250v 3752 f07 r start v in 16v 8ma gnd c start system input (v s ) lt3752-1 vhk (housekeeping supply output) ? + figure 7. micropower start-up from high system input the start-up capacitor can be calculated as: c start(min) = i hkeep + i drive ( ) (max) ,? t hss(max) v droop(min) where: i hkeep = housekeeping i q (not switching) i drive = (f osc /2.13) ? q g ) f osc = full-scale controller switching frequency q g = gate charge (v gs = v in )(hout mosfet) t hss = housekeeping output voltage soft-start time v droop = 16v(clamp) C v in(off) or v in(onoffhyst) the start-up resistor can be calculated as: r start(max) = v s(max) C v in(on)(max) i start(max) ?k where: v s(max) = maximum system input voltage v in(on)(max) = maximum v in pin turn on threshold i start(max) = maximum v in i q for part start-up k > 1.0 reduces r start and v in charge-up time 1.250v(+) 1.215v(?) 3752 f06 r1 r2 ovlo ovlo to uvlo_v sec pin r3 system input (v s ) lt3752/lt3752-1 ? + lt3752/lt3752-1 3752fb
23 for more information www.linear.com/lt3752 applications information worst-case values should be used to calculate the c start and r start required to guarantee start-up and to turn on in the time required. example: (lt3752-1) for v s(min) = 75v, v in(on)(max) = 10.4v i start(max) = 265a, i hkeep(max) = 4.6ma q g = 8nc (at v in = 10v), f osc = 150khz t hss(max) = 4ms, v droop(min) = 1.61v c start(min) = 4.6ma + 71khz ? 8nc ( ) ? 4ms 1.61v = 12.8f choose 14.7f ( ) r start(max) = 75v C 10.4v 265a ?k = 243k for k = 1.0 ( ) the r start(max) value should be chosen with higher k values until the charge-up time for c start is acceptable. in most cases, c start will be charged to the 16v clamp on the lt3752-1 v in pin before system input reaches its uvlo(+) threshold (figure 4). this will allow an extra 5.6v for v droop in the c start equation, allowing a smaller c start value and hence a faster start-up time. the trade-off of lower r start is greater power dissipa - tion, given by: p rstart = (v s C v in ) 2 /r start for r start = 200k, v s(max) = 150v, v in = 10v (back driven from housekeeping supply) p rstart = (150 C 10) 2 /200k = 98mw. programming switching frequency the switching frequency for the housekeeping supply and the main forward converter are programmed using a resistor, r t , connected from analog ground (pin 18) to the rt pin. table 1 shows typical f osc vs r t resistor values. the value for r t is given by: r t = 8.39 ? x ? (1 + y) where, x = (10 9 /f osc ) C 365 y = (300khz C f osc )/10 7 (f osc < 300khz) y = (f osc C 300khz)/10 7 (f osc > 300khz) example: for f osc = 200khz, r t = 8.39 ? 4635 ? (1 + 0.01) = 39.28k (choose 39.2k) the lt3752/lt3752-1 include frequency foldback at start- up (see figures 3 and 4). in order to make sure that a sync input does not override frequency foldback during start-up, the sync function is ignored until ss1 pin reaches 2.2v. both the housekeeping and forward controllers run synchronized to each other and in phase, with or without the sync input. table 1. r t vs switching frequency (f osc ) switching frequency (khz) r t (k) 100 82.5 150 53.6 200 39.2 250 30.9 300 24.9 350 21 400 18.2 450 15.8 500 14 synchronizing to an external clock the lt3752 / lt3752-1 internal oscillator can be synchro - nized to an external clock at the sync pin. sync pin high level should exceed 1.8v for at least 100ns and sync pin low level should fall below 0.6v for at least 100ns. the sync pin frequency should be set equal to or higher than the typical frequency programmed by the r t pin. an f sync /f osc ratio of x (1.0 < x < 1.25) will reduce the externally programmed slope compensation by a factor of 1.2x. if required, the external resistor r islp can be reprogrammed higher by a factor of 1.2x. (see current sensing and programmable slope compensation). lt3752/lt3752-1 3752fb
24 for more information www.linear.com/lt3752 applications information the part injection locks the internal oscillator to every ris - ing edge of the sync pin. if the sync input is removed at any time during normal operation the part will simply change switching frequency back to the oscillator frequency programmed by the r t resistor. this injection lock method avoids the possible issues from a pll method which can potentially cause a large drop in frequency if sync input is removed. during soft-start the sync input is ignored until ss1 ex - ceeds 2.2v. during soft-stop the sync input is completely ignored. if the sync input is to be used, recall that the programmable duty cycle clamp d vsec is dependent on the switching frequency of the part (see section programming duty cycle clamp). r ivsec should be reprogrammed by 1/x for an f sync /f osc ratio of x. intv cc regulator bypassing and operation the intv cc pin is the output of an internal linear regula - tor driven from v in and provides the supply for onboard gate drivers. the lt3752 intv cc provides a regulated 7v supply for gate drivers aout, sout, out and hout. the lt3752-1 intv cc provides a regulated 10v supply for gate drivers aout, sout and out. intv cc should be bypassed with a 4.7f low esr, x7r or x5r ceramic capacitor to power ground to ensure stability and to provide enough charge for the gate drivers. the intv cc regulator has a minimum 35ma output cur - rent limit. this current limit should be considered when c ho osing the switching frequency and capacitance loading on each gate driver. average current load on the intv cc pin for a single gate driver driving an external mosfet is given as : i intvcc = f osc ? q g where: f osc = controller switching frequency q g = gate charge (v gs = intv cc ) while the intv cc 50ma output current limit is sufficient for lt3752/lt3752-1 applications, efficiency and internal power dissipation should also be considered. intv cc can be externally overdriven by the housekeeping supply to improve efficiency, remove power dissipation from within the ic and provide more than 35ma output current ca - pability. any overdrive level should exceed the regulated int v cc level but not exceed 16v. in the case of a short-circuit fault from intv cc to ground, each ic reduces the intv cc output current limit to typically 23ma. the intv cc regulator has an undervoltage lockout rising threshold, uvlo(+), which prevents gate driver switching until intv cc reaches 4.75v (7v for lt3752-1) and maintains switching until intv cc falls below a uvlo(C) threshold of 4.6v (6.8v for lt3752-1). for v in levels close to or below the intv cc regulated level, the intv cc linear regulator may enter dropout. the result - ing lower intv cc level will still allow gate driver switching as long as intv cc remains above intv cc uvlo(C) levels. see the typical performance characteristics section for intv cc performance vs v in and load current. housekeeping controller the lt3752/lt3752-1 include an internal constant fre - quency, current mode, pwm controller for creating a housekeeping supply (see the block diagram and figure?8). connected as a flyback converter with multiple outputs, the housekeeping supply is able to efficiently provide bias to both primary and secondary ics. it eliminates the need to generate bias supplies from auxiliary windings in the main forward transformer, reducing the complexity, size and cost of the transformer. figure 8. housekeeping supply v in v in intv cc v aux * intv cc vhk ? ? ltc3752/lt3752-1 intv cc hcomp hout hi sense gnd hfb r hislp r1 r2 r hsense *optional isolated supply for secondary side 3752 f08 ? lt3752/lt3752-1 3752fb
25 for more information www.linear.com/lt3752 applications information integrating the housekeeping controller saves cost and space and allows switching frequency to be inherently synchronized to the main forward converter. the housekeeping supply can be used to overdrive the intv cc pin to take power outside of the part, improve efficiency, provide more drive current and optimize the intv cc level. it can also be used as a bootstrap bias to the v in pin as described in the section lt3752-1 part start-up. the housekeeping supply also allows bias to any secondary side ic before the main forward converter starts switching. this removes the need for external start- up circuitry on the secondary side. alternative methods involve powering secondary side ics directly from the output voltage of the forward converter. this can cause issues depending on the minimum and maximum allowed input voltages for each ic. housekeeping: operation the lt3752/lt3752-1 housekeeping controller opera - tion is best described by referring to the block diagram and figure 8. the housekeeping controller uses a 0.7a gate driver at hout to control an external n-channel mosfet. when current in the primary winding of the flyback transformer exceeds a level commanded by hcomp and sensed at the hi sense pin, the duty cycle of the hout is terminated. stored energy in the transformer is delivered to the output during the off time of hout. the housekeep - ing output voltage is programmed using a resistor divider to the hfb pin. a transconductance amplifier monitors the error signal between hfb pin and a 1.0v reference to control hcomp level and hence peak switch current. a simple rc network from hcomp pin to ground provides compensation. overcurrent protection exists for the exter - nal switch when 98mv is sensed at the hi sense pin. this causes a low power hiccup mode (repeated retry cycles of shutdown followed by soft-start) until the overcurrent condition is removed. housekeeping: soft-start/shutdown during start-up of the lt3752/lt3752-1, the housekeeping controller has a built-in soft-start of approximately 2.2ms. the time will vary depending on the hcomp level needed to achieve regulation. the housekeeping controller is shut down and the internal soft-start capacitor is discharged for any of the following conditions (typical values): (1) uvlo_v sec < 1.25v (and ss1 < 0.15v) :soft-stop shutdown (2) uvlo_v sec < 0.4v :micropower shutdown (3) ovlo > 1.250v :system input ovlo (4) hi sense > 98mv :housekeeping overcurrent (5) int v cc < x, > 16.5v :intv cc uvlo, ovlo (6) t j > 170c :thermal shutdown (7) v in < y :v in pin uvlo (x = 4.6v, y = 5.5v for lt3752) (x = 6.8v, y = 7.6v for lt3752-1) housekeeping: programming output voltage the output voltage, v hk , of the housekeeping controller is programmed using a resistor divider between v hk and the hfb pin (figure 8) using the equation: v hk = 1v ? 1 + r1 r2 ? ? ? ? the hfb pin bias current is typically 85na. housekeeping: programming cycle-by-cycle peak inductor current and slope compensation the housekeeping controller limits cycle-by-cycle peak current in the external switch and primary winding of the flyback transformer by sensing voltage at a resistor (r hisense ) connected in the source of the external n - chan - nel mosfet (figure 8). this sense voltage is compared to a sense threshold at the hi sense pin, controlled by hcomp with an upper limit of 79mv. since there is only one sense line from the positive terminal of the sense resistor, any parasitic resistance in ground side will increase its effec - tive value and reduce available peak switch current. for operation in continuous mode and above 50% duty cycle, required slope compensation can be programmed by adding a resistor r hislp in series with the hi sense pin. a ramped current always flows out of the hi sense pin. the current starts from 2a at 0% duty cycle and ramps to 52a at 100% duty cycle. minimize capacitance on this pin. lt3752/lt3752-1 3752fb
26 for more information www.linear.com/lt3752 applications information for a desired peak switch current, the value for r hisense should be calculated using a 30% derated 79mv sense threshold with the effects of slope compensation included: r hsense = 52.5mv C ?v hslp i lp(peak) where: ?v hslp = (2a + d ? (62.5a) ? r hislp ) i lp(peak) = cycle-by-cycle peak current in primary winding d = switch duty cycle r hislp = slope compensation programming resistor if operating in continuous mode above 50% duty cycle, a good starting value for r hislp is 499 which gives a 26mv total drop in current comparator threshold at 80% duty cycle. an f sync /f osc ratio of x (1.0v < x < 1.25) will reduce the externally programmed slope compensation by a factor of 1.2x. if required, the external resistor r hislp can be reprogrammed higher by a factor of 1.2x. housekeeping: adaptive leading edge blanking blanking of the hi sense signal on the leading edge of hout is adaptive to allow a wide range of mosfets. the blanking occurs from the start of hout rise and waits until hout has reached within 1v of its maximum level (intv cc for lt3752, v in for lt3752-1) before adding an additional fixed 100ns of blanking. housekeeping: overcurrent hiccup mode to protect the housekeeping controller during a short- to-ground fault on the housekeeping output voltage, a 98mv fixed overcurrent threshold exists at the hi sense pin to discharge the internal soft-start capacitor and enter a hiccup (retry) mode. this hiccup mode significantly reduces the average power in the external components compared to continued cycle-by-cycle switching at the 79mv threshold. having already calculated the r hsense resistor for peak cycle-by-cycle current, the typical hiccup mode over current level in the switch and primary winding is given by: i lp(overcurrent) = 98mv C ?v hslp r hsense where: ?v hslp = (2a + d ? (62.5a) ? r hislp ) d = switch duty cycle r hislp = slope compensation programming resistor r hsense = current sense resistor housekeeping: output overvoltage and power good the housekeeping controller monitors its supplies ris - ing output voltage v hk via the hfb pin and determines power good (pgood(+)) when v hk reaches 96% of its programmed value. 10s after confirmation of pgood, the circuitry for the lt3752/lt3752-1 forward controller is activated. the ss1 pin is allowed to begin charging and eventually allows the forward converter to start switching. if v hk falls below 92% of its programmed level (pgood(C)), the ss1 pin is discharged and forward controller circuitry is disabled. to limit housekeeping output overvoltage, v hk , the house- keeping controller overrides its own regulation loop and immediately stops switching if its output voltage exceeds 20% of its programmed value. this is especially impor - tant when using the housekeeping supply to bias other ics. the for ward controller is still allowed to switch. the housekeeping controller returns to normal regulation loop control when its output voltage, v hk , falls to less than 15% above its programmed value. housekeeping: transformer turns ratio and leakage inductance the external resistor divider used to set the output voltage of the housekeeping supply provides a relative freedom in selecting the transformer turns ratio to suit a given lt3752/lt3752-1 3752fb
27 for more information www.linear.com/lt3752 applications information application. simple integer turns ratios can be used which allow off-the-shelf transformers (see example circuits in the typical applications section). turns ratios can be chosen on the basis of desired duty cycle. however, the input and output levels, turns ratio and flyback leakage spike must be considered for the breakdown rating of the mosfet. transformer leakage inductance causes a voltage spike to occur after the switch turns off. in some cases a snubber circuit will be required to limit this spike. housekeeping: operating without this supply the housekeeping supply is highly recommended for providing local bias voltages for both the primary and secondary sides (to improve efficiency, simplify the main transformer design and ensure all ics are activated even for v out = 0v). the lt3752 (not lt3752-1) housekeeping supply components can be omitted (not populated) if an extra winding already exists from the main transformer to create an auxiliary supply. care must be taken that the auxiliary supply (for either the primary side or secondary side or both) does not affect proper operation. a resistor divider (figure 8) should now be connected directly from intv cc to supply the hfb pin with a ratio : r1/r2 = 3 (example : r1 = 10k, r2 = 3.32k). this ratio ensures hfb >> 0.96v (typical pgood level to enable ss1 and the forward converter). (a) at intv cc = 4.75v (uvlo(+)), hfb = 1.2v. (b) at intv cc = 7v (regulated), hfb = 1.7v. (c) at intv cc = 8v (overdriven), hfb = 2v. care should be taken not to exceed hfb = 3v. forward controller the lt3752/lt3752-1 are primary side, current mode, pwm controllers optimized for use in a synchronous forward converter with active clamp reset. each ic can be used in a fully regulated forward converter application. in addition, they can still operate if damage occurs to the feedback pathno secondary side error amplifier or opto-couplerby using an accurate, programmable volt- second clamp to regulate duty cycle inversely proportional to transformer input voltage. adaptive leading edge blanking plus programmable extended blanking the lt3752/lt3752-1 provide a 2a gate driver at the out pin to control an external n-channel mosfet for main power delivery in the forward converter (figure 10). during gate rise time and sometime thereafter, noise can be generated in the current sensing resistor connected to the source of the mosfet. this noise can potentially cause a false trip of sensing comparators resulting in early switch turn off and in some cases re-soft-start of the system. to prevent this, lt3752/lt3752-1 provide adaptive leading edge blanking of both oc and i sensep signals to allow a wide range of mosfet q g ratings. in addition, a resistor r tblnk connected from t blnk pin to analog ground (pin?18) programs an extended blanking duration (figure 9). figure 9. adaptive leading edge blanking plus programmable extended blanking (adaptive) leading edge blanking (programmable) extended blanking 7.32k r tblnk 249k t blnk = 50ns + (2.2ns ? r tblnk ) current sense delay 220ns k 3752 f09 out lt3752/lt3752-1 3752fb
28 for more information www.linear.com/lt3752 v in v in intv cc v out m1 r sense 3752 f10 r islp ? ? ltc3752/lt3752-1 intv cc comp out oc i sensep from regulation loop i sensen gnd figure 10. current sensing and programmable slope compensation applications information adaptive leading edge blanking occurs from the start of out rise and completes when out reaches within 1v of its maximum level (intv cc for lt3752, v in for lt3752-1). an extended blanking then occurs which is programmable using the r tblnk resistor given by: t blnk = 50ns + 2.2ns k ? r tblnk ? ? ? ? , 7.32k < r tblnk < 249k adaptive leading edge blanking minimizes the value re - quired for r tblnk . increasing r tblnk further than required increases m1 minimum on time (figure 10). in addition, the critical volt-second clamp (d vsec ) is not blanked. therefore, if d vsec decreases far enough (in soft start foldback and at maximum input voltage) m1 may turn off before blanking has completed. since oc and i sensep signals are only seen when m1 is on (and after blanking has completed), r tblnk value should be limited by: (2.2ns/k)r tblnk < t vsec(min) C t adaptive C 50ns where, t vsec(min) = 10 9 (d vsec (max) /(fold.fosc)) (input (min) /input (max) ) fold = f osc and d vsec foldback ratio (for out pin) ( = 4 for lt3752 , = 2 for l t3752-1) t adaptive = out pin rise time to intv cc C 1v example: for figure 20 circuit, d vsec(max) = 0.77, input (min)/(max) = 17.4v/74v, fold = 4, t adaptive = 23ns and f osc = 240khz, t vsec(min) = 10 9 (0.77/(4 ? 2.4 ? 10 5 )) ? 17.4/74 = 188ns (2.2ns/1k)r tblnk < 188 C 23 C 50 r tblnk < 52.5k (actual circuit uses 34k) current sensing and programmable slope compensation the lt3752/lt3752-1 command cycle-by-cycle peak current in the external switch and primary winding of the forward transformer by sensing voltage across a resistor connected in the source of the external n-channel mosfet (figure 10). the sense voltage across r sense is compared to a sense threshold at the i sensep pin, controlled by comp pin level. two sense inputs, i sensep and i sensen , are provided to allow a kelvin connection to r sense . for operation in con - tinuous mode and above 50% duty cycle, required slope compensation can be programmed by adding a resistor , r islp , in series with the i sensep pin. a ramped current always flows out of the i sense pin. the current starts from 2a at 0% duty cycle and linearly ramps to 33a at 80% duty cycle. a good starting value for r islp is 1.5k which gives a 41mv total drop in current comparator threshold at 65% duty cycle. the comp pin commands an i sensep threshold between 0mv and 220mv. the 220mv allows a large slope com - pensation voltage drop to exist in r islp without effecting the programming of r sense to set maximum operational currents in m1. an f sync /f osc ratio of x (1.0 < x < 1.25) will reduce the externally programmed slope compensa - tion by a factor of 1.2x. if required, the external resistor r islp can be reprogrammed higher by a factor of 1.2x. overcurrent: hiccup mode the lt3752/lt3752-1 use a precise 96mv sense thresh - old at the oc pin to detect excessive peak switch current (figure 10). during an overload condition switching lt3752/lt3752-1 3752fb
29 for more information www.linear.com/lt3752 applications information stops immediately and the ss1/ss2 pins are rapidly discharged. the absence of switching reduces the sense voltage at the oc pin, allowing ss1/ss2 pins to recharge and eventually attempt switching again. the part exists in this hiccup mode as long as the overcurrent condition exists. this protects the converter and reduces power dissipation in the components (see hard stop in the applications information section). the 96mv peak switch current threshold is independent of the voltage drop in r islp used for slope compensation. output dc load current to trigger hiccup mode: load(overcurrent) = n p n s ? 96mv r isense ? ? ? ? ? ? ? 1/2 i ripple(p-p) ( ) where: n p = forward transformer primary turns n s = forward transformer secondary turns i ripple(p-p) = output inductor peak-to-peak ripple current r isense should be programmed to allow maximum dc load current for the application plus enough margin during load transients to avoid overcurrent hiccup mode. programming maximum duty cycle clamp: d vsec (volt-second clamp) unlike other converters which only provide a fixed maxi - mum duty cycle clamp, the lt3752/lt3752-1 provide an accurate programmable maximum duty cycle clamp (d vsec ) on the out pin which moves inversely with system input. d vsec provides a duty cycle guardrail to limit the volt-seconds-on product over the entire natural duty cycle range (figures 11 and 12). this limits the drain voltage required for complete transformer reset. a resistor r ivsec from the ivsec pin to analog ground (pin 18) programs d vsec . d vsec (out pin duty cycle clamp) = 0.725 ? r ivsec 51.1k ? f osc 300 ? 1.25 uvlo_v sec where: r ivsec = programming resistor at ivsec pin f osc = switching frequency (khz) uvlo_v sec = resistor divided system input voltage r ivsec can program any d vsec required at minimum system input. d vsec will then follow natural duty cycle as v in varies. maximum programmable d vsec is typi - figure 11. volt-second (d vsec ) clamp 3752 f12 r1 r2 uvlo_v sec to ovlo pin r3 r ivsec system input lt3752/lt3752-1 ivsec rt r t figure 12. programming d vsec t on_vsec t on out t d = t on /t 3752 f11 (programmed by r ivsec ) dv sec = t on_vsec /t dv sec = ?duty cycle guardrail? lt3752/lt3752-1 3752fb
30 for more information www.linear.com/lt3752 applications information cally 0.75 but may be further limited by the transformer design and voltage ratings of components connected to the drain of the primary side power mosfet (swp). see voltage calculations in the lo side and hi side active clamp topologies sections. if system input voltage falls below it's uvlo threshold the part will enter soft-stop with continued switching. the lt3752/lt3752-1 include an intelligent circuit which prevents d vsec from continuing to rise as system input voltage falls (see soft-stop). without this, too large a d vsec would require extremely high reset voltages on the swp node to properly reset the transformer. the uvlo_v sec pin maximum operational level is the lesser of v in C 2v or 12.5v. the lt3752/lt3752-1 volt-second clamp architecture is superior to an external rc network connected from system input to trip an internal comparator threshold. the rc method suffers from external capacitor error, part- to-part mismatch between the rc time constant and the ics switching period, the error of the internal comparator threshold and the nonlinearity of charging at low input voltages. the lt3752/lt3752-1 use the r ivsec resistor to define the charge current for an internal timer capacitor to set an out pin maximum on-time, t on(vsec) . the voltage across r ivsec follows uvlo_v sec pin voltage (divided down from system input voltage). hence, r ivsec current varies linearly with input supply. the lt3752/lt3752-1 also trim out internal timing capacitor and comparator threshold errors to optimize part-to-part matching between t on(vsec) and t. d vsec open loop control: no opto-coupler, error amplifier or reference the accuracy of the programmable volt-second clamp (d vsec ) safely controls v out if open loop conditions exist such as no opto-coupler, error amplifier or reference on the secondary side. d vsec controls the output of the converter by controlling duty cycle inversely proportional to system input. if d vsec duty cycle guardrail is programmed x% above natural duty cycle, v out will only increase by x% if a closed loop system breaks open. this volt-second clamp is operational over a 10:1 system input voltage range. see d vsec versus uvlo_v sec pin voltage in the typical performance characteristics section. r ivsec : open pin detection provides safety the lt3752/lt3752-1 provide an open-detection safety feature for the r ivsec pin. if the r ivsec resistor goes open circuit the part immediately stops switching. this prevents the part from running without the volt-second clamp in place. transformer reset: active clamp technique the lt3752/lt3752-1 include a 0.4a gate driver at the aout pin to allow the use of an active clamp transformer reset technique (figures 13, 17). the active clamp method improves efficiency and reduces voltage stress on the main power switch, m1. by switching in the active clamp capacitor only when needed, the capacitor does not lose its charge during m1 on-time. by allowing the active clamp capacitor, c cl , to store the average voltage required to reset the transformer, the main power switch sees lower drain voltage. an imbalance of volt-seconds will cause magnetizing cur - rent to walk upwards or downwards until the active clamp capacitor is charged to the optimal voltage for proper transformer reset. the voltage rating of the capacitor will depend on whether the active clamp capacitor is actively switched to ground (figure 13) or actively switched to lt3752/lt3752-1 3752fb
31 for more information www.linear.com/lt3752 20s/div i mag 1a/div swp 50v/div 3752 f14 applications information system input (figure 17). in an active clamp reset topol- ogy, volt-second balance requires: v in ? d = (swp C v in ) ? (1 C d) where: v in = transformer input supply d = (v out /v in ) ? n = switch m1 duty cycle v out = output voltage (including the voltage drop contribution of m4 catch diode during m1 off) n = transformer turns ratio = n p /n s swp = m1 drain voltage duty cycle (%) 20 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 50 70 3752 f15 30 40 60 80 active clamp capacitor voltage normalized to 50% duty cycle lo side active clamp topology figure 15. lo side v ccl vs duty cycle (normalized to 50% duty cycle) figure 14. active clamp reset: magnetizing current and m1 drain voltage figure 13. lo side active clamp topology c cl l leak l leak l mag fsw csw ? ? v d d1r1 c1 m2 m4 m3 m1 swp out v in ?v in v out ?v out aout lt3752 fg ltxxxx cg 3752 f13 lt3752/lt3752-1 3752fb
32 for more information www.linear.com/lt3752 figure 16. hi side v ccl vs duty cycle (normalized to 50% duty cycle) duty cycle (%) 20 active clamp capacitor voltage normalized to 50% duty cycle 1.5 3752 f16 1.0 0.5 40 60 30 50 70 2.0 2.5 1.3 0.8 1.8 2.3 80 hi side active clamp topology figure 17. hi side active clamp topology applications information lo side active clamp topology (lt3752) the steady-state active clamp capacitor voltage, v ccl , required to reset the transformer in a lo side active clamp topology (figure 13) can be approximated as the drain-to- source voltage (v ds ) of switch m1, given by: v ccl (lo side): (a) steady state: v ccl = swp = v ds = 1 1? d ? ? ? ? ? v in = v in 2 v in ? v out ? n ( ) ( ) (b) transient: during load transients, duty cycle and hence v ccl may increase. replace d with d vsec in the equation above to calculate transient v ccl values. see the previous section programming duty cycle clampCd vsec . the d vsec guard - rail can be programmed as close as 5% higher than d but may require a larger margin to improve transient response. as shown in figure 15, the maximum steady-state value for v ccl may occur at minimum or maximum input volt - age. hence v ccl should be calculated at both input voltage levels and the largest of the two calculations used. m1 drain should be rated for a voltage greater than the above steady-state v ds calculation due to tolerances in duty cycle, load transients, voltage ripple on c cl and leakage inductance spikes. c cl should be rated higher due to the effect of voltage coefficient on capacitance value. a typical choice for c cl is a good quality x7r capacitor. m2 should have a v ds rating greater than v ccl since the bottom plate of c cl is Cv ccl during m1 on and m2 off. for high input voltage applications, the limited v ds rating of available p-channel mosfets might require changing from a lo side to hi side active clamp topology. for the lo side active clamp topology in steady state, during m1 on time, magnetizing current (i mag ) increases from a negative value to a positive value (figure 14). when m1 turns off, magnetizing current charges swp until it reaches v ccl plus the voltage drop of the m2 body diode. at this c cl l leak l leak swp l mag fsw csw ? ? ? ? v d d1 ?v in c2 t4 c1 m2 m4 m1 m3 r1 out v in ?v in v out ?v out aout lt3752-1 fg ltxxxx cg 3752 f17 lt3752/lt3752-1 3752fb
33 for more information www.linear.com/lt3752 applications information moment the active clamp capacitor is passively switched in to ground (due to the forward conduction of m2 body diode) and the drain voltage increases at a slower rate due to the loading of c cl . swp above v in causes i mag to reduce from a positive value towards zero (dv swp /dt = 0). as i mag becomes negative it begins to discharge the swp node. switching in m2 before i mag reverses, actively connects the bottom plate of c cl to ground and allows swp to be discharged slowly. the resulting swp waveform during m1 off-time appears as a square wave with a superimposed sinusoidal peak representing ripple voltage on c cl . the switch m2 experiences near zero voltage switching (zvs) since only the body diode voltage drop appears across it at switch turn on. hi side active clamp topology (lt3752-1) for high input voltage applications the v ds rating of avail - able p-channel mosfets might not be high enough to be used as the active clamp switch in the lo side active clamp topology (figure 13). an n-channel approach using the hi side active clamp topology (figure 17) should be used. this topology requires a gate drive transformer or a simple gate drive opto-coupler to drive the n-channel mosfet (m2) for switching in the active clamp capacitor from swp to v in . the m1 drain voltage calculation is the same as in the lo side active clamp case and m1 should be rated in a similar manner. the voltage across the clamp capacitor in the hi side architecture, however, is lower by v in since it is referenced to v in . the steady-state active clamp capacitor voltage v ccl to reset the transformer in a hi side active clamp topology can be approximated by: v ccl (hi side): (a) steady state: v ccl = v reset = v ds C v in = d 1? d ? ? ? ? ? v in = v in ? v out ? n v in ? v out ? n ( ) (b) transient: during load transients, duty cycle and hence v ccl may increase. replace d with d vsec in the equation above to calculate transient v ccl values. d vsec guardrail can be programmed as close as 6% higher than d but may require a larger margin to improve transient response. see the previous section programming duty cycle clampCd vsec . c cl should be rated for a voltage higher than the above steady-state calculation due to tolerances in duty cycle, load transients, voltage ripple on c cl and the effect of voltage coefficient on capacitance value. a typical choice for c cl is a good quality (x7r) capacitor. when using a gate drive transformer to provide control of the active clamp switch (m2), the external components c1, c2, r1, d1 and t4 are required. t4 size will increase for lower programmed switching frequencies due to a minimum volt-second requirement. alternatively, a simple gate driver opto-coupler can be used as a switch to control m2, for a smaller solution size. the input supply capacitor for the gate drive opto-coupler is easily charged using the housekeep - ing supply of the lt3752-1. common component values are shown in the typical applications section. active clamp capacitor v alue and voltage ripple the active clamp capacitor value should be chosen based on the amount of voltage ripple which can be tolerated by components attached to swp. lower c cl values will create larger voltage ripple (increased drain voltage for the primary side power mosfet) but will require less swing in magnetizing current to move the active clamp capacitor during duty cycle changes. choosing too high a value for the active clamp capacitor (beyond what is needed to keep ripple voltage to an acceptable level) will require unneces - sary additional flux swing during transient conditions. for systems with flux swing detection, too high a value for the active clamp capacitor will trigger the detection system early and degrade transient response. lt3752/lt3752-1 3752fb
34 for more information www.linear.com/lt3752 applications information another factor to consider is the resonance between c cl and the magnetizing inductance (l mag ) of the main transformer. an rc snubber (r s , c s ) in parallel with c cl will dampen the sinusoidal ringing and limit the peak voltages at the primary side mosfet drain during input/load transients. check circuit performance to determine if the snubber is required. component values can be approximated as: c cl (active clamp capacitance) = 10 l mag ? (1Cd min ) 2 ? ? f osc ? ? ? ? ? ? 2 where, d min = (v out /v in(max) ) ? n p /n s and (if needed), c s (snubber capacitance) = 6 ? c cl r s (snubber resistance) = (1/(1-d max )) ? (l mag /c cl ) where, d max = ( v out /v in(min) ) ? n p /n s check the voltage ripple on swp during steady-state operation. c cl voltage ripple can be estimated as: v ccl(ripple) = v ccl ? (1-d) 2 /(8 ? c cl ? l mag ? f osc 2 ) where, d = (v out /v in ) ? (n p /n s ) v ccl = v in /(1-d) (lo side active clamp topology) v ccl = d ? v in /(1-d) (hi side active clamp topology) example : for v in = 36v, v out = 12v, n p /n s = 2, v ccl = 108v (lo side active clamp topology), c cl = 22nf, l mag = 100h, f osc = 250khz, v ccl(ripple) = 108(0.33) 2 /(8(22 ? 10 C9 )(10 C4 )(2.5 ? 10 4 ) 2 ) = 10.7v the transformer is typically chosen to operate at a maximum flux density that is low enough to avoid excessive core losses. this also allows enough headroom during input and load transients to move the active clamp capacitor at a fast enough rate to keep up with duty cycle changes. active clamp mosfet selection the selection of active clamp mosfet is determined by the maximum levels expected for the drain voltage and drain current. the active clamp switch (m2) in a either a lo side or hi side active clamp topology has the same bvdss requirements as the main n-channel power mosfet. the current requirements are divided into two categories : (a) drain current this is typically less than the main n-channel power mosfet because the active clamp mosfet sees only magnetizing current, estimated as : peak i mag (steady state) = (1/2) ? (n p /n s ) ? (v out / l mag ) ? (1/f osc ) where, l mag = main transformers magnetizing inductance example (lt3752) : for v out =12v, n p /n s = 2, f osc = 250khz and l mag = 100h, peak i mag = 0.48a. this value should be doubled for safety margin due to variations in l mag , f osc and transient conditions. (b) body diode current the body diode will see reflected output current as a pulse every time the main n-channel power mosfet turns off. this is due to residual energy stored in the transformer's leakage inductance. the body diode of the active clamp mosfet should be rated to withstand a forward pulsed current of: i d(max) = (n s /n p ) (i out(max) + (i l(ripple)(p-p) /2)) where, i l(ripple)(p-p) = output inductor ripple current = (v out / (l out ? f osc )) ? (1C(v out /v in )(n p /n s )) i out(max) = maximum output load current lt3752/lt3752-1 3752fb
35 for more information www.linear.com/lt3752 applications information programming active clamp switch timing: aout to out (t ao ) and out to aout (t oa ) delays the timings t ao and t oa represent the delays between aout and out edges (figures 1 and 2) and are programmed by a single resistor, r tao , connected from analog ground (pin 18) to the t ao pin. once t ao is programmed for the reasons given below, t oa will be automatically generated. front-end timing t ao (m2 off, m1 on) = aout(edge)-to-out(rising) = 50ns + 3.8ns ? r tao 1k ? ? ? ? , 14.7k < r tao < 125k in order to minimize turn-on transition loss in m1 the drain of m1 should be as low as possible before m1 turns on. to achieve this, aout should turn m2 off a delay of t ao before out turns m1 on. this allows the main transformers magnetizing current to discharge m1 drain voltage quickly towards v in before m1 turns on. as swp falls below v in , however, the rectifying diodes on the secondary side are typically active and clamp the swp node close to v in . if enough leakage inductance exists, however, the clamping action on swp by the secondary side will be delayedpotentially allowing the drain of m1 to be fully discharged to ground just before m1 turns on. even with this delay due to the leakage inductance, l mag needs to be low enough to allow i mag to be negative enough to slew swp down to ground before m1 turns on. if achievable, m1 will experience zero voltage switching (zvs) for highest efficiency. as will be seen in a later sec - tion entitled primary-side power mosfet selection, m1 transition loss is a significant contributor to m1 losses. back-end timing t oa (m1 off, m2 on) is automatically generated = out(falling)-to-aout(edge) = 0.9 ? t ao t oa should be checked to ensure m2 is not turned on until m1 and m3 are turned off. programming synchronous rectifier timing: sout to out (t so ) and out to sout (t os ) delays the lt3752/lt3752-1 include a 0.4a gate driver at the sout pin to send a control signal via a pulse transformer to the secondary side of the forward converter for syn - chronous rectification (see figures 1 and 2). for the highest efficiency , m4 should be turned on whenever m1 is turned off. this suggests that sout should be a non- overlapping signal with out with ver y small non-overlap times. inherent timing delays, however, which can vary from application to application, can exist between out to csw and between sout to cg. possible shoot-through can occur if both m1 and m4 are on at the same time, resulting in transformer and/or switch damage. front-end timing: t so (m4 off, m1 on) = sout(falling)-to-out(rising) delay = t so = t ao C t as = 3.8ns ? (r tas C r tao ) where: t as = 50ns + (3.8ns ? r tas /1k) , 14.7k < r tas < 125k, t ao = 50ns + (3.8ns ? r tao /1k), 14.7k < r tao < 125k, t so is defined by resistors r tas and r tao connected from analog ground (pin 18) to their respective pins t as and t ao . each of these resistor defines a delay referenced to the aout edge at the start of each cycle. r tao was already programmed based on requirements defined in the previous section programming aout to out delay. r tas is then programmed as a delay from aout to sout to fulfill the equation above for t so . by choosing r tas less than or greater than r tao , the delay between sout falling and out rising can be programmed as positive or nega - tive. while a positive delay can always be programmed for t so , the ability to program a negative delay allows for improved efficiency if out(rising)-to-csw(rising) delay is larger than sout(falling)-to-cg(rising) delay. lt3752/lt3752-1 3752fb
36 for more information www.linear.com/lt3752 applications information back-end timing: t os (m1 off, m4 on) = out (falling)-to-sout (rising) delay = t os = 35ns + (2.2ns ? r tos /1k), 7.32k < r tos < 249k the timing resistor, r tos , defines the out (falling)-to-sout (rising) delay. this pin allows programming of a positive delay, for applications which might have a large inherent delay from out fall to sw2 fall. soft-start (ss1, ss2) the lt3752/lt3752-1 use ss1 and ss2 pins for soft starting various parameters (figures 3, 4 and 18). ss1 soft starts internal oscillator frequency and d vsec (maximum duty cycle clamp). ss2 soft starts comp pin voltage to control output inductor peak current. using separate ss1 and ss2 pins allows the soft-start ramp of oscillator frequency and d vsec to be independent of comp pin soft-start. typically ss1 capacitor (c ss1 ) is chosen as 0.47f and ss2 capaci - tor (c ss2 ) is chosen as 0.1f. soft-start charge currents are 11.5a for ss1 and 21a for ss2. ss1 is allowed to start charging (soft-start) if all of the following conditions exist (typical values) : (1) uvlo_v sec > 1.25v: system input not in uvlo (2) ovlo < 1.215v: system input not in ovlo (3) hfb > 0.96v: housekeeping supply valid (4) oc < 96mv: no over current condition (5) x < intv cc < 16v: intv cc valid (6) t j < 165c: junction temperature valid (7) v in > y: v in pin valid (x = 4.75v, y = 5.8v for lt3752) (x = 7.0v, y = 9.5v for lt3752-1) ss1 = 0v to 1.25v (no switching). this is the ss1 range for no switching for the forward converter. ss2 = 0v. ss1 > 1.25v allows ss2 to begin charging from 0v. ss1 = 1.25v to 2.45v (soft-start f osc , d vsec ). this is the ss1 range for soft-starting f osc and d vsec folded back from 22% (50% for lt3752-1) to 100% of their programmed levels. fold back of f osc and d vsec reduces effective minimum duty cycle for the primary side mosfet. this allows inductor current to be controlled at low output voltages during start-up. ss1 ramp rate is chosen slow enough to ensure f osc and d vsec foldback lasts long enough for the converter to take control of inductor current at low output voltages. in ad - dition, slower ss1 ramp rate increases the non-switching period during an output short to ground fault (over current hiccup mode) to reduce average power dissipation (see hard-stop). ss2 = 0v to 1.6v (soft-start comp pin). this is the ss2 range for soft-starting comp pin from approximately 1v to 2.6v . ss2 ramp rate is chosen fast enough to allow a (slower) soft-start control of comp pin from a secondar y side opto-coupler controller. ss1 soft-start non-switching period (0v to 1.25v) = 1.25v ? c ss1 /11.5a ss1 soft-start f osc , d vsec period (1.25v to 2.45v) = 1.2v ? c ss1 /11.5a ss2 soft-start comp period (0v to 1.6v) = 1.6v ? c ss2 /21a soft-stop (ss1) the lt3752/lt3752-1 gradually discharge the ss1 pin (soft-stop) when a system input uvlo occurs or when an external soft-stop shutdown command occurs (0.4v < uvlo_v sec < 1.25v). during ss1 soft-stop the converter continues to switch, folding back f osc , d vsec and comp pin voltage (figures 3, 4 and 18). soft-stop discharge current is 10.5a for ss1. soft-stop provides: (1 ) act ive control of the secondary winding during output discharge for clean shutdown in self-driven applica- tions. (2) controlled discharge of the active clamp capacitor to minimize magnetizing current swing during restart. lt3752/lt3752-1 3752fb
37 for more information www.linear.com/lt3752 applications information ss1: 2.45v to 1.25v (soft-stop f osc , d vsec , comp). this is the ss1 range for soft-stop folding back of: (1) f osc and d vsec from 100% to 22% (50% for lt3752-1) of their programmed levels. (2 ) comp pin (100% to 0% of commanded peak current). ss1 soft-stop f osc , d vsec , comp period (2.45v to 1.25v) = 1.2v ? c ss1 /10.5a ss1 < 1.25v. forward converter stops switching and ss2 pin is discharged to 0v using 2.8ma. ss1 = 1.25v to 0v: when ss1 falls below 0.15v the internal ss1 latch is reset. if all faults are removed, ss1 begins charging again. if faults still remain, ss1 discharges to 0v. ss1 soft-stop non-switching period (1.25v to 0v) = 1.25v ? c ss1 /10.5a d vsec rises as system input voltage falls in order to provide a maximum duty cycle guardrail (volt-second clamp). when system input falls below it's uvlo thresh - old, however, this triggers a soft-stop with the converter continuing to switch. it is important that d vsec no longer increases even though system input voltage may still be falling. the lt3752/lt3752-1 achieve an upper clamp on d vsec by clamping the minimum level for the i vsec pin to 1.25v. as ss1 pin discharges during soft-stop it folds back d vsec . as d vsec falls below the natural duty cycle of the converter, the converter loop follows d vsec . if the system input voltage rises (i vsec pin rises) during soft- stop the volt-second clamp circuit further reduces d vsec . the i.c. chooses the lowest d vsec commanded by either the i vsec pin or the ss1 soft-stop function. hard-stop (ss1, ss2) switching immediately stops and both ss1 and ss2 pins are rapidly discharged (figure 18. hard-stop) if any of the following faults occur (typical values): (1) uvlo_v sec < 0.4v: micropower shutdown (2) ovlo > 1.250v: system input ovlo (3) hfb < 0.92v: housekeeping supply uvlo (4) oc > 96mv: over current condition (5) intv cc < x(uvlo), > 16.5v (ovlo) (6) t j > 170c: thermal shutdown (7) v in < y: v in pin uvlo (x = 4.6v, y = 5.5v for lt3752) (x = 6.8v, y = 7.6v for lt3752-1) switching stops immediately for any of the faults listed above. when ss1 discharges below 0.15v it begins charg - ing again if all faults have been removed. for an over cur - rent fault triggered by oc > 96mv, the disable of switching will cause the oc pin voltage to fall back below 96mv. this will allow ss1 and ss2 to recharge and eventually attempt switching again. if the over current condition still exists, oc pin will exceed 96mv again and the discharge/ charge cycle of ss1 and ss2 will repeat in a hiccup mode. the non-switching dead time period during hiccup mode reduces the average power seen by the converter in an over current fault condition. the dead time is dominated by ss1 recharging from 0.15v to 1.25v. non-switching period in over current (hiccup mode): = 1.1v ? c ss1 /11.5a out, aout, sout pulse-skipping mode during load steps, initial soft-start, end of soft-stop or light load operation (if the forward converter is designed to operate in dcm), the loop may require pulse skipping on the out pin. this occurs when the comp pin falls below its switching threshold. if the comp pin falls below it's switching threshold while out is turned on, the lt3752/ lt3752-1 will immediately turn out off ; both aout and sout will complete their normal signal timings referenced from the out falling edge. if the comp pin remains below it's switching threshold at the start of the next switching cycle, the lt3752/lt3752-1 will skip the next out pulse and therefore also skip aout and sout pulses. for aout control, this prevents the active clamp capacitor from be - lt3752/lt3752-1 3752fb
38 for more information www.linear.com/lt3752 ing accidentally discharged during missing out pulses and/or causing reverse saturation of the transformer. for sout control, this prevents the secondary side syn - chronous rectifier controller from incorrectly switching between forward fet and synchronous fet conduction. the l t3752/lt3752-1 correctly re-establish the required aout, sout control signals if the out signal is required for the next cycle. aout timeout during converter start-up in soft-start, the switching fre - quency and maximum duty cycle clamp d vsec are both folded back. while this correctly reduces the effective minimum on time of the out pin (to allow control of induc - tor current for very low output voltages during start-up), this means the aout pin on time duration can be large. in order to ensure the active clamp switch controlled by aout does not stay on too long, the lt3752/lt3752-1 have an internal 15s timeout to turn off the aout signal. this prevents the active clamp capacitor from being connected across the transformer primary winding long enough to create reverse saturation. main transformer selection the lt3752/lt3752-1 simplify the design of the main transformer and output inductor by removing the need for any auxiliary windings. any bootstrap supplies required for the primary side or bias supplies required for the secondary side can all be provided by the housekeeping dc/dc controller included in the lt3752/lt3752-1. (see housekeeping controller in the applications information section). applications information figure 18. ss1, ss2 and comp pin voltages during faults, soft-start and soft-stop comp range 2.6v 2.6v 0v 0v 1.25v 0.15v 0.25v comp 1.25v switching threshold ss2 soft starts comp 0v 1v comp ss2 ss1 2.6v hard stop soft-start (when all conditions satisfied) (1) uvlo_v sec > 1.25v (2) ovlo < 1.215v (3) hfb > 0.96v (4) oc < 96mv (5) x < intv cc < 16v (6) t j < 165c (7) v in > y (x = 4.75v, y = 5.8v: lt3752) (y = 7.0v, y = 9.5v: lt3752-1) soft-stop (0.4v < uvlo_v sec < 1.25) (1) external soft-stop shutdown (2) system input uvlo hard stop (faults) (1) uvlo_v sec < 0.4v (2) ovlo > 1.25v (3) hfb < 0.92v (4) oc > 96mv (5) intv cc < x, > 16.5v (6) t j > 170c (7) v in < y (x = 4.6v, y = 5.5v: lt3752) (x = 6.8v, y = 7.6v: lt3752-1) 3752 f18 ss1 soft stops f osc , d vsec and comp ss1 soft starts f osc and d vsec ss1 latch reset threshold lt3752/lt3752-1 3752fb
39 for more information www.linear.com/lt3752 the selection of the main transformer will depend on the applications requirements : isolation voltage, power level, maximum volt-seconds, turns ratio, component size, power losses and switching frequency. transformer construction using the planar winding technol - ogy is typically chosen for minimizing leakage inductance and reducing component height. t ransformer core type is usually a ferrite material for high frequency applications. find a family of transformers that meet both the isolation and power level requirements of the application. the next step is to find a transformer within that family which is suitable for the application. the subsequent thought pro - cess for the transformer design will include : (1) secondary turns (n s ), core losses, temperature rise, flux density, switching frequency (2) primary turns (n p ), maximum duty cycle and reset voltages (3) copper losses the expression for secondary turns (n s ) is given by, n s = 10 8 v out /(f osc ? a c ? b m ) where, a c = cross-sectional area of the core in cm 2 b m = maximum ac flux density desired for flux density, choose a level which achieves an accept - able level of core loss/temperature rise at a given switching frequency . the transformer data sheet will provide cur ves of core loss versus flux density at various switching fre - quencies. the data sheet will also provide temperature rise versus core loss. while choosing a value for bm to avoid excessive core losses will usually allow enough headroom for flux swing during input / load transients, still make sure to stay well below the saturation flux density of the transformer core. if needed, increasing n s will reduce flux density. after calculating n s , the number of primary turns (n p ) can be calculated from, n p = n s ? d max v in(min) /v out where, v in(min) = minimum system input voltage d max = maximum switch duty cycle at v in(min) (typically chosen between 0.6 and 0.7) at minimum input voltage the converter will run at a maxi - mum duty cycle d max . a higher transformer turns ratio (n p /n s ) will create a higher d max but it will also require higher voltages at the drain of the primary side switch to reset the transformer (see previous sections lo side active clamp topology and hi side active clamp topology). d max values are typically chosen between 0.6 and 0.7. even for a given d max value, the loop must also provide protection against duty cycles that may excessively exceed d max during transients or faults. while most converters only provide a fixed duty cycle clamp, the lt3752/lt3752-1 provide a programmable maximum duty cycle clamp d vsec that also moves inversely with input voltage. the resulting function is that of a programmable volt- second clamp. this allows the user to choose a transformer turns ratio for d max and then customize a maximum duty cycle clamp d vsec above d max for safety. d vsec then follows the natural duty cycle of the converter as a safety guardrail (see previous section programming duty cycle clamp). after deciding on the particular transformer and turns ratio, the copper losses can then be approximated by, p cu = d ? i(load) (max) 2 (r sec + (n s /n p ) 2 r pri ) where, d = switch duty cycle (choose nominal 0.5) i(load) (max) = maximum load current applications information lt3752/lt3752-1 3752fb
40 for more information www.linear.com/lt3752 r pri = primary winding resistance r sec = secondary winding resistance if there is a large difference between the core losses and the copper losses then the number of secondary turns can be adjusted to achieve a more suitable balance. the number of primary turns should then be recalculated to maintain the desired turns ratio. primary-side power mosfet selection the selection of the primary-side n-channel power mosfet m1 is determined by the maximum levels expected for the drain voltage and drain current. in addition, the power losses due to conduction losses, gate driver losses and transition losses will lead to a fine tuning of the mosfet selection. if power losses are high enough to cause an unacceptable temperature rise in the mosfet then several mosfets may be required to be connected in parallel. the maximum drain voltage expected for the mosfet m1 follows from the equations previously stated in the active clamp topology sections: v ds (m1) = v in 2 /(v in C (v out ? n)) the mosfet should be selected with a bv dss rating ap- proximately 20% greater than the above steady state v ds calculation due to tolerances in duty cycle, load transients, voltage ripple on c cl and leakage inductance spikes. a mosfet with the lowest possible voltage rating for the application should be selected to minimize switch on re - sistance for improved efficiency. in addition, the mosfet should be selected with the lowest gate charge to further minimize losses. mosfet m1 losses at maximum output current can be approximated as : p m1 = p conduction + p gatedriver + p transition (i) p conduction = (n p /n s ) ? (v out /v in ) ? (n s /n p ? i out(max) ) 2 ? r ds(on) note: the on resistance of the mosfet, r ds(on) , in- creases with the mosfets junction temperature. r ds(on) should therefore be recalculated once junction tem - perature is known. a final value for r ds(on) and therefore p conduction can be achieved from a few iterations. (ii) p gatedriver = (q g ? intv cc ? f osc ) where, q g = gate charge (v gs = intv cc ) (iii) p transition = p turn_off + p turn_on ( 0 if zvs) (a) p turn_off = (1/2)i out(max) (n s /n p )(v in /1-d) (q gd /i gate ) ? f osc where, q gd = gate to drain charge i gate = 2a source/sink for out pin gate driver (b) p turn_on = (1/2)i out(max) (n s /n p )(v ds )(q gd /i gate ) ? f osc where, v ds = m1 drain voltage at the beginning of m1 turn on v ds typically sits between v in and 0v (zvs) during programmable timing t ao , negative i mag discharges m1 drain swp towards v in (figure 1). zvs is achieved if enough leakage inductance existsto delay the second - ary side from clamping m1 drain to v in and if enough energy is stored in l mag to discharge swp to 0v during that delay. (see programming active clamp switch timing: aout to out (t ao )). synchronous control (sout) the lt3752 / lt3752-1 use the sout pin to communicate synchronous control information to the secondary side synchronous rectifier controller (figure 19). the isolating transformer (t sync ), coupling capacitor (c sync ) and resis - tive load (r sync ) allow the ground referenced sout signal to generate positive and negative signals required at the sync input of the secondary side synchronous rectifier controller. for the typical lt3752/lt3752-1 applications operating with an lt8311, c sync is 220pf, r sync is 560 and t sync is typically a pulse pe-68386nl. applications information lt3752/lt3752-1 3752fb
41 for more information www.linear.com/lt3752 typically choose c sync between 220pf and 1nf. r sync should then be chosen to obey : (1) sout max /100ma r sync (l mag /c sync ) where, sout max = intv cc l mag = t syncs magnetizing inductance 100ma = sout gate driver minimum source current and (2) r sync ? c sync (C1) ? y/(ln (z/sout max )) where, y = sync minimum pulse duration (50ns; lt8311) z = |sync level to achieve y| (2v: l t8311) even though the lt3752/lt3752-1 intv cc pin is allowed to be over driven by as much as 15.4v using the house - keeping supply, sout max level should be designed to not cause t sync output to exceed the maximum ratings of the lt8311s sync pin. cost/space reduction : if discontinuous conduction mode (dcm) operation is acceptable at light load, the lt8311 has a preactive mode which controls the synchronous mosfets without t sync , c sync , r sync or the lt3752/ lt3752-1 timing resistors r tas , r tos (leave open). output inductor value the choice of output inductor value l out will depend on the amount of allowable ripple current. the inductor ripple current is given by: i l(ripple)(p-p) = ?i l = (v out /(l out ? f osc )) ? (1 C (v out /v in )(n p /n s )) the lt3752/lt3752-1 allow very large ?i l values (low l out values) without the worry of insufficient slope compensa - tionby allowing slope compensation to be programmed with an external resistor in series with the i sensep pin (see current sensing and programmable slope compensation). larger ?i l will allow lower l out , reducing component size, but will also cause higher output voltage ripple and core losses. for lt3752/lt3752-1 applications, ?i l is typically chosen to be 40% of i out(max) . output capacitor selection the choice of output capacitor value is dependent on output voltage ripple requirements given by : ?v out ?i l (esr + (1/(8 ? f osc ? c out )) where, ?i l = output inductor ripple current i l(ripple)(p-p) esr = effective series resistance (of c out ) f osc = switching frequency c out = output capacitance this gives: c out = ?i l /(8 ? f osc ? ( ?v out C ?i l ? esr)) typically c out is made up of a low esr ceramic capacitor(s) to minimize ?v out . additional bulk capacitance is added in the form of electrolytic capacitors to minimize output voltage excursions during load steps. input capacitor selection the active clamp forward converter demands pulses of current from the input due to primary winding current and magnetizing current. the input capacitor is required to provide high frequency filtering to achieve an input voltage as close as possible to a pure dc source with low ripple voltage. for low impedance input sources and medium to low voltage input levels, a simple ceramic capacitor with low esr should suffice. it should be rated to operate at a worst case rms input current of : i cin(rms) = (n s /n p ) i out(max) /2 figure 19. sout pulse transformer 3752 f19 c sync 220pf r sync 560 sync (secondary side controller) t sync sout (lt3752/lt3752-1) 2 1 3 5 6 4 ? ? ? ? applications information lt3752/lt3752-1 3752fb
42 for more information www.linear.com/lt3752 a small 1f bypass capacitor should also be placed close to the ic between v in and gnd. as input voltage levels increase, any use of bulk capacitance to minimize input ripple can impact on solution size and cost. in addition, inputs with higher source impedance will cause an increase in voltage ripple. in these applications it is recommended to include an lc input filter. the output impedance of the input filter should remain below the negative input impedance of the dc/dc forward converter. pcb layout / thermal guidelines for proper operation, pcb layout must be given special attention. critical programming signals must be able to co-exist with high dv/dt signals. compact layout can be achieved but not at the cost of poor thermal management. the following guidelines should be followed to approach optimal performance. 1. ensure that a local bypass capacitor is used (and placed as close as possible) between v in and gnd for the controller ic(s). 2. the critical programming resistors for timing (pins t ao ,t as ,t os ,t blnk , ivsec and rt) must use short traces to each pin. each resistor should also use a short trace to connect to a single ground bus specifically connected to pin 18 of the ic (gnd). 3. the current sense resistor for the forward converter must use short kelvin connections to the i sensep and i sensen pins. the current sense resistor for the housekeeping supply should have its ground connection as close as possible to the power ground (pgnd) pin 38. 4. high dv/dt lines should be kept away from all timing resistors, current sense inputs, hcomp/comp pins, uvlo_vsec/ovlo pins and both hfb and fb feedback traces. 5. gate driver traces (hout, aout, sout, out) should be kept as short as possible. 6. when working with high power components, multiple parallel components are the best method for spread - ing out power dissipation and minimizing temperature rise. in particular, multiple copper layers connected by vias should be used to sink heat away from each power mosfet . 7. keep high switching current pgnd paths away from signal ground. also minimize trace lengths for those high current switching paths to minimize parasitic inductance. applications information lt3752/lt3752-1 3752fb
43 for more information www.linear.com/lt3752 figure 20. 18v to 72v, 12v/12.5a, 150w active clamp isolated forward converter efficiency vs load current applications information r4 49.9k r5 22.6k r3 1.82k r6 7.32k r7 34k r8 71.5k r9 31.6k r23 100k r24 100k r10 2.8k r11 10k t1: champs g45ah2-0404-04 t2: bh electronics l00-3250 t3: pulse pe-68386nl l1: champs pqi2050-6r8 d1, d2, d3: bas516 d4: central semi cmmr1u-02 r13 560 r28 3.16k r27 100k v aux v aux sync v in gnd fb lt8311 pgood r14 2k r15 0.006 r16 10k r18 0.15 r17 499 c10 2.2f c9 2.2f intv cc v aux m5 zvn4525e6 si2325ds d3 t2 d2 d1 m1 bsc077n12ns3 m2 m3 fdms86101 bsc077n12ns3 r25 100 r12 1.1k r26 1k 2.2nf c2 0.33f c3 22nf ps2801-1 c4 22nf c5 4.7f c11 2.2f c13 22f 16v 2 c24 2.2nf 250v v out 12v 12.5a c14 470f 16v c12 4.7f c17 220nf 3752 f20a c18 68pf c19 4.7nf c6 220pf t3 c16 1f t ao t as t os t blnk ivsec rt ss1 ss2 hcomp fb comp opto intv cc timer ss comp csp pmode intv cc intv cc sout i sensen i sensep out v in aout hi sense hout oc r2 5.9k r1 100k uvlo_v sec lt3752 sync c7 100nf c8 15nf t1 4:4 m4 r20 499k r29 13.7k l1 6.8h r30 100k r31 11.3k csn fg fsw cg csw r21 100 r22 100 r38 20k + ?? ?? ? ? ? c1 4.7f 100v 3 v in 18v to 72v gnd ovlo hfb d4 c28 68pf load current (a) 0 efficiency (%) 96 94 92 90 88 86 63 3752 f20b 15129 24v in 48v in 72v in lt3752/lt3752-1 3752fb
44 for more information www.linear.com/lt3752 typical applications 18v to 72v, 12v/12.5a, 150w no-opto, active clamp isolated forward converter v out vs load current (no-opto) efficiency vs load current r4 49.9k r5 22.6k r3 1.82k r6 7.32k r7 34k r8 60.4k r9 31.6k r10 2.8k r11 10k t1: champs g45ah2-0404-04 t2: bh electronics l00-3250 t3: pulse pe-68386nl l1: champs pqi2050-6r8 d1, d2, d3: bas516 d4: central semi cmmr1u-02 r13 560 v aux v aux sync v in gnd fb lt8311 pgood r14 2k r15 0.006 r16 10k r18 0.15 r17 499 c10 2.2f c9 2.2f intv cc v aux m5 zvn4525e6 d3 t2 d2 d1 m1 bsc077n12ns3 fdms86101 r12 1.1k 2.2nf c2 0.33f c3 22nf c4 22nf c5 4.7f c11 2.2f c13 22f 16v 2 v out 12v 12.5a c14 470f 16v c12 4.7f 3752 ta02 c6 220pf t3 t ao t as t os t blnk ivsec rt ss1 ss2 hcomp fb comp opto intv cc timer ss comp csp pmode intv cc intv cc sout i sensen i sensep out v in aout hi sense hout oc r2 5.9k r1 100k uvlo_v sec lt3752 sync c7 100nf c8 15nf t1 4:4 r20 499k l1 6.8h csn fg fsw cg csw r21 100 r22 100 + ?? ?? ? ? ? c1 4.7f 100v 3 v in 18v to 72v gnd ovlo hfb si2325ds m3 m4 bsc077n12ns3 m2 c24 2.2nf 250v r38 20k d4 load current (a) 0 v out (v) 14.0 13.5 13.0 12.5 12.0 11.0 10.5 11.5 10.0 42 3752 ta02a 12 8 10 6 v in = 70v v in = 60v v in = 48v v in = 36v v in = 20v load current (a) 0 efficiency (%) 96 94 92 90 88 86 63 3752 ta02b 15129 24v in 48v in 72v in lt3752/lt3752-1 3752fb
45 for more information www.linear.com/lt3752 typical applications 150v to 400v, 12v/16.7a, 200w active clamp isolated forward converter efficiency vs load current r4 95.3k r5 40.2k r3 2.94k r6 13k r7 100k r8 124k r9 78.7k r23 22k r24 22k r10 22k r11 10k t1: champs lt80r2-12ac-3124005 t2: wrth 750817020 t3: pulse pe-68386nl l1: coilcraft agp2923-153 d1: central semi cmr1u-10 d2, d3, d5: bas516 d4: central semi cmmr1u-02 r13 560 r28 3.16k r27 100k v aux sync v in gnd fb lt8311 pgood r14 2k r15 0.022 r18 0.15 r17 499 r35 374k r36 374k c10 4.7f c9 10f intv cc v aux intv cc m5 bsp300 d3 t2 d2 m1 ipd65r25oc6 ipd60r1k4c6 m3 m2 r25 100 r12 806 r26 1.2k 2.2nf c2 0.47f c3 0.22f ps2801-1 c4 3.3nf c5 4.7f c11 2.2f c13 33f 16v 4 c24 10nf 250v v out 12v 16.7a c14 330f 16v c12 4.7f c17 1f 3752 ta03 c18 100pf c19 22nf c6 220pf t3 c16 1f t ao t as t os t blnk ivsec rt ss1 ss2 hcomp fb comp opto intv cc v aux timer ss comp csp pmode intv cc intv cc sout i sensen i sensep out v in aout hi sense hout oc r2 5.76k r1 499k r34 499k uvlo_v sec lt3752-1 sync rjk0653dpb 2 t1 31:5 c20 10f d5 m4 fdms86200 3 r20 432k r29 5.11k l1 15h r30 100k r31 11.3k csn fg fsw cg csw r21 100 d4 r22 100 r38 10k r38 0.002 c27 120pf + ?? ?? ? ? ? d1 r16 4.2 c1 2.2f 630v v in 150v to 400v gnd ovlo hfb cathode anode acpl-w346 v ee v out v cc c21 0.22f c8 47nf 630v c15 10nf 630v r19 402 c28 68pf load current (a) 0 efficiency (%) 96 95 94 93 92 90 89 91 88 85 87 86 52.5 3752 ta03a 17.5 10 12.5 15 7.5 v in = 150v v in = 250v v in = 350v v in = 400v lt3752/lt3752-1 3752fb
46 for more information www.linear.com/lt3752 typical applications 150v to 400v, 12v/16.7a, 200w no-opto, active clamp isolated forward converter v out vs load current (no-opto) efficiency vs load current r4 95.3k r5 40.2k r3 2.94k r6 13k r7 100k r8 107k r9 78.7k r10 22k r11 10k t1: champs lt80r2-12ac-3124005 t2: wrth 750817020 t3: pulse pe-68386nl l1: coilcraft agp2923-153 d1: central semi cmr1u-10 d2, d3, d5: bas516 d4: central semi cmmr1u-02 r13 560 v aux sync v in gnd fb lt8311 pgood r14 2k r15 0.022 r18 0.15 r17 499 r35 374k r36 374k c10 4.7f c9 10f intv cc v aux intv cc m5 bsp300 d3 t2 d2 m1 ipd65r25oc6 ipd60r1k4c6 m3 m2 r12 806 2.2nf c2 0.47f c3 0.22f c4 3.3nf c5 4.7f c11 2.2f c13 33f 16v 4 v out 12v 16.7a c14 330f 16v c12 4.7f v aux 3752 ta04 c6 220pf t3 t ao t as t os t blnk ivsec rt ss1 ss2 hcomp fb comp opto intv cc timer ss comp csp pmode intv cc intv cc sout i sensen i sensep out v in aout hi sense hout oc r2 5.76k r1 499k r34 499k uvlo_v sec lt3752-1 sync rjk0653dpb 2 t1 31:5 c20 10f d5 m4 fdms86200 3 r20 432k l1 15h csn fg fsw cg csw + ?? ?? ? ? ? d1 acpl-w346 r16 4.2 c1 2.2f 630v v in 150v to 400v gnd ovlo hfb cathode anode v ee v out v cc c21 0.22f c8 47nf 630v c15 10nf 630v r19 402 r38 0.002 r21 100 r22 100 c27 120pf c24 10nf 250v d4 r38 10k load current (a) 0 v out (v) 14.0 13.5 13.0 12.5 12.0 11.5 10.0 11.0 10.5 42 3752 ta04a 18 8 1210 14 16 6 v in = 150v v in = 250v v in = 350v v in = 400v load current (a) 0 efficiency (%) 96 95 94 93 92 90 89 91 88 85 87 86 52.5 3752 ta04b 17.5 10 12.5 15 7.5 v in = 150v v in = 250v v in = 350v v in = 400v lt3752/lt3752-1 3752fb
47 for more information www.linear.com/lt3752 typical applications 150v to 400v, 12v/16.7a, 200w, active clamp isolated forward converter (using gate drive transformer for high side active clamp) efficiency vs load current r4 95.3k r5 40.2k r3 2.94k r6 13k r7 100k r8 124k r9 78.7k r23 22k r24 22k r10 22k r11 10k t1: champs lt80r2-12ac-3124005 t2: wrth 750817020 t3: pulse pe-68386nl t4: ice gt05-111-100 l1: coilcraft agp2923-153 d1: central semi cmr1u-10 d2, d3, d5: bas516 d4: central semi cmmr1u-02 r13 560 r28 3.16k r27 100k v aux sync v in gnd fb lt8311 pgood r14 2k r15 0.022 r18 0.15 r16 10k c23 3.3nf r17 499 r35 374k c22 220nf r37 100 r36 374k c10 4.7f c9 10f intv cc v aux d1 c21 470pf m5 bsp300 d3 t2 t4 d2 m1 ipd65r25oc6 ipd60r1k4c6 m3 m2 r25 100 r12 806k r26 1.2k 2.2nf c2 0.47f c3 0.22f ps2801-1 c4 3.3nf c5 4.7f c11 2.2f c13 33f 16v 4 v out 12v 16.7a c14 330f 16v c12 4.7f v aux c17 1f 3752 ta05 c18 100pf c19 22nf c6 220pf t3 c16 1f t ao t as t os t blnk ivsec rt ss1 ss2 hcomp fb comp opto intv cc timer ss comp csp pmode intv cc intv cc sout i sensen i sensep out v in aout hi sense hout oc r2 5.76k r1 499k r34 499k uvlo_v sec lt3752-1 sync rjk0653dpb 2 t1 31:5 c20 10f d5 m4 fdms86200 3 r20 432k r29 5.11k l1 15h r30 100k r31 11.3k csn fg fsw cg csw + ?? ?? ? ? ? c1 2.2f 630v v in 150v to 400v gnd ovlo hfb c8 47nf 630v c15 10nf 630v r19 402 ?? r21 100 r22 100 r38 0.002 c27 120pf c24 10nf 250v d4 r38 10k c28 68pf load current (a) 0 efficiency (%) 96 95 94 93 92 90 89 91 88 85 87 86 52.5 3752 ta05a 17.5 10 12.5 15 7.5 v in = 150v v in = 250v v in = 350v v in = 400v lt3752/lt3752-1 3752fb
48 for more information www.linear.com/lt3752 typical applications 150v to 400v, 12v/16.7a 200w, no-opto, active clamp isolated forward converter (using gate drive transformer for high side active clamp) v out vs load current (no-opto) efficiency vs load current r4 95.3k r5 40.2k r3 2.94k r6 13k r7 100k r8 107k r9 78.7k r10 22k r11 10k t1: champs lt80r2-12ac-3124005 t2: wrth 750817020 t3: pulse pe-68386nl t4: ice gt05-111-100 l1: coilcraft agp2923-153 d1: central semi cmr1u-10 d2, d3, d5: bas516 d4: central semi cmmr1u-02 r13 560 v aux sync v in gnd fb lt8311 pgood r14 2k r15 0.022 r18 0.15 r16 10k c23 3.3nf r17 499 r35 374k c22 220nf r37 100 r36 374k c10 4.7f c9 10f intv cc v aux d1 c21 470pf m5 bsp300 d3 t2 t4 d2 m1 ipd65r25oc6 ipd60r1k4c6 m3 m2 r12 806 2.2nf c2 0.47f c3 0.22f c4 3.3nf c5 4.7f c11 2.2f c13 33f 16v 4 v out 12v 16.7a c14 330f 16v c12 4.7f 3752 ta06 c6 220pf t3 t ao t as t os t blnk ivsec rt ss1 ss2 hcomp fb comp opto intv cc v aux timer ss comp csp pmode intv cc sout i sensen i sensep out v in aout hi sense hout oc r2 5.76k r1 499k r34 499k uvlo_v sec lt3752-1 sync rjk0653dpb 2 t1 31:5 c20 10f d5 m4 fdms86200 3 r20 432k l1 15h csn fg fsw cg csw + ?? ?? ? ? ? c1 2.2f 630v v in 150v to 400v gnd ovlo hfb c8 47nf 630v c15 10nf 630v r19 402 ?? r21 100 r38 0.002 r22 100 c27 120pf c24 10nf 250v d4 r38 10k load current (a) 0 v out (v) 14.0 13.5 13.0 12.5 12.0 11.5 10.0 11.0 10.5 42 3752 ta06a 18 8 1210 14 16 6 v in = 150v v in = 250v v in = 350v v in = 400v load current (a) 0 efficiency (%) 96 95 94 93 92 90 89 91 88 85 87 86 52.5 3752 ta06b 17.5 10 12.5 15 7.5 v in = 150v v in = 250v v in = 350v v in = 400v lt3752/lt3752-1 3752fb
49 for more information www.linear.com/lt3752 typical applications 75v to 150v, 24v/14a 340w active clamp isolated forward converter (using gate drive transformer for high side active clamp) efficiency vs load current r4 93.1k r5 53k r3 5.76k r6 10k r7 80.1k r8 82.5k r9 52.3k r23 22k r24 22k r10 22k r11 10k t1: champs lt80r2-12ac-1006 t2: wrth 750817020 t3: pulse pe-68386nl t4: ice gt05-111-100 l1: coilcraft agp2923-153 d1: central semi cmr1u-10 d2, d3, d5: bas516 d4: central semi cmmr1u-02 r13 560 r28 3.16k r27 100k v aux sync v in gnd fb lt8311 pgood r14 2k r15 0.0075 r18 0.15 r16 10k c23 3.3nf r17 499 r35 102k c22 220nf r37 100 r36 102k c10 4.7f c9 10f intv cc v aux d1 c21 470pf m5 bsp300 d3 t2 t4 d2 m1 ipb200n25n3 irfl214 m3 m2 r25 100 r12 806 r26 1.2k 2.2nf c2 0.47f c3 0.22f ps2801-1 c4 3.3nf c5 4.7f c11 2.2f c13 22f 25v 4 v out 24v 14a c14 470f 25v c12 4.7f c17 0.33f v aux 3752 ta07 c18 100pf c19 22nf c6 220pf t3 c16 1f t ao t as t os t blnk ivsec rt ss1 ss2 hcomp fb comp opto intv cc timer ss comp csp pmode intv cc intv cc sout i sensen i sensep out v in aout hi sense hout oc r2 6.04k r1 6.98k r34 698k uvlo_v sec lt3752-1 sync bsc047n08ns3 2 t1 10:6 c20 10f d5 m4 ipb072n15n3g r20 365k r29 5.11k l1 15h r30 100k r31 5.36k csn fg fsw cg csw + ?? ?? ? ? ? c1 2.2f 250v v in 75v to 150v gnd ovlo hfb c8 15nf 250v c15 4.7nf 250v r19 1k ?? r21 100 r22 100 r38 0.003 c27 120pf c24 10nf 250v d4 r38 10k c28 68pf load current (a) 0 efficiency (%) 96 95 94 93 92 91 86 90 89 88 87 2.5 3752 ta07a 15 7.5 10 12.5 5 v in = 75v v in = 100v v in = 125v v in = 150v lt3752/lt3752-1 3752fb
50 for more information www.linear.com/lt3752 package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 4.75 (.187) ref fe38 (ab) tssop rev b 0910 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 19 pin numbers 23, 25, 27, 29, 31, 33 and 35 are removed 20 ref 9.60 ? 9.80* (.378 ? .386) 38 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.50 (.0196) bsc 0.17 ? 0.27 (.0067 ? .0106) typ recommended solder pad layout 0.315 0.05 0.50 bsc 4.50 ref 6.60 0.10 1.05 0.10 4.75 ref 2.74 ref 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package package variation: fe38 (31) 38-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1665 rev b) exposed pad variation ab lt3752/lt3752-1 3752fb
51 for more information www.linear.com/lt3752 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 06/14 minor typographical changes throughout data sheet. all b 07/15 changed absolute maximum ss2 rating to 16v. changed absolute maximum ss1 rating to 3v. changed output low level in shutdown conditions to intv cc = 3v. changed aout rise and fall times. changed sout rise and fall times. changed ss2 discharge current conditions to ss2 = 2.5v. changed ss2 charge current conditions to ss2 = 1.5v. changed hout rise and fall times. 3 3 3 5 6 6 6 7 lt3752/lt3752-1 3752fb
52 for more information www.linear.com/lt3752 ? linear technology corporation 2014 lt 0715 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt3752 related parts typical application part number description comments lt8311 preactive secondary synchronous and opto control for forward converters optimized for use with primary-side lt3752/-1, lt3753 and lt8310 controllers ltc3765/ltc3766 synchronous no-opto forward controller chip set with active clamp reset direct flux limit, supports self starting secondary forward control ltc3722/ltc3722-2 synchronous full bridge controllers adaptive or manual delay control for zero voltage switching, adjustable synchronous rectification timing lt3748 100v isolated flyback controller 5v v in 100v, no opto flyback , msop-16 with high voltage spacing lt3798 off-line isolated no-opto flyback controller with active pfc v in and v out limited only by external components 75v to 150v, 24v/14a 340w no-opto, active clamp isolated forward converter efficiency vs load current v out vs load current (no-opto) r4 93.1k r5 53k r3 5.76k r6 10k r7 80.1k r8 75k r9 52.3k r10 22k r11 10k t1: champs lt80r2-12ac-1006 t2: wrth 750817020 t3: pulse pe-68386nl t4: ice gt05-111-100 l1: coilcraft agp2923-153 d1: central semi cmr1u-10 d2, d3, d5: bas516 d4: central semi cmmr1u-02 r13 560 v aux sync v in gnd fb lt8311 pgood r14 2k r15 0.0075 r18 0.15 r16 10k c23 3.3nf r17 499 r35 c22 220nf r37 100 r36 c10 4.7f c9 10f intv cc v aux d1 c21 470pf m5 bsp300 d3 t2 t4 d2 m1 ipb200n25n3 irfl214 m3 m2 r12 806 2.2nf c2 0.47f c3 0.1f c4 3.3nf c5 4.7f c11 2.2f c13 22f 25v 4 v out 24v 14a c14 470f 25v c12 4.7f 3752 ta08 c6 220pf t3 t ao t as t os t blnk ivsec rt ss1 ss2 hcomp fb comp opto intv cc timer ss comp csp pmode intv cc intv cc sout i sensen i sensep out v in aout hi sense hout oc r2 6.04k r1 6.98k r34 698k uvlo_v sec lt3752-1 sync bsc047n08ns3 2 t1 10:6 c20 10f d5 m4 ipb072n15n3g r20 432k l1, 15h csn fg fsw cg csw + ?? ?? ? ? ? c1 2.2f 250v v in 75v to 150v gnd ovlo hfb c8 15nf 250v c15 4.7nf 250v r19 1k ?? r21 100 r38 0.003 r22 100 c27 120pf c24 10nf 250v d4 r38 10k load current (a) 0 v out (v) 28 27 26 25 24 20 23 22 21 2 3752 ta08a 16 12 14 6 8 10 4 v in = 75v v in = 100v v in = 125v v in = 150v load current (a) 0 efficiency (%) 96 95 94 93 92 91 86 90 89 88 87 2.5 3752 ta08b 15 7.5 10 12.5 5 v in = 75v v in = 100v v in = 125v v in = 150v lt3752/lt3752-1 3752fb

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